These hardware register definitions are common for all K3, remove duplicate data them by moving them to hardware.h.
While here do some minor whitespace cleanup + grouping.
Signed-off-by: Andrew Davis afd@ti.com --- arch/arm/mach-k3/am642_init.c | 1 - arch/arm/mach-k3/include/mach/am62_hardware.h | 17 ------------ arch/arm/mach-k3/include/mach/am64_hardware.h | 26 ++++--------------- arch/arm/mach-k3/include/mach/am6_hardware.h | 25 +++--------------- arch/arm/mach-k3/include/mach/hardware.h | 19 +++++++++++++- .../arm/mach-k3/include/mach/j721e_hardware.h | 25 +++--------------- .../mach-k3/include/mach/j721s2_hardware.h | 25 +++--------------- 7 files changed, 32 insertions(+), 106 deletions(-)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 8428322ed9..0e30cc47f5 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -23,7 +23,6 @@ #include <mmc.h> #include <dm/root.h>
-#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRLMMR_MCU_RST_CTRL 0x04518170
static void ctrl_mmr_unlock(void) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 9118d05204..278beb587f 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -44,23 +44,6 @@ /* Backup Bootmode USB Config macros */ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
-/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism - * shared register definitions. The same registers are also used for - * PADCFG_MMR lock/kick-mechanism. - */ -#define CTRLMMR_LOCK_KICK0 0x1008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK1 0x100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index e06e1f9532..6c9332e2bd 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -7,12 +7,13 @@ #ifndef __ASM_ARCH_AM64_HARDWARE_H #define __ASM_ARCH_AM64_HARDWARE_H
+#define PADCFG_MMR1_BASE 0x000f0000 +#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRL_MMR0_BASE 0x43000000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) - -#define PADCFG_MMR1_BASE 0xf0000
-#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 @@ -35,23 +36,6 @@
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
-/* - * The CTRL_MMR and PADCFG_MMR memory space is divided into several - * equally-spaced partitions, so defining the partition size allows us to - * determine register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
/* Use Last 2K as Scratch pad */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index f533e22e06..f9f32918f7 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -13,8 +13,10 @@ #endif
#define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) @@ -28,27 +30,6 @@ #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9 #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9)
-#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 028482b3b6..d6d2cf6dc2 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -27,7 +27,7 @@ #endif
/* Assuming these addresses and definitions stay common across K3 devices */ -#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 @@ -43,6 +43,23 @@ #define SYS_STATUS_SUB_TYPE_MASK (0xf << 8) #define SYS_STATUS_SUB_TYPE_VAL_FS 0xa
+/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + #define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT"
struct rom_extended_boot_data { diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index b98f0a82f1..032cb2657a 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -12,9 +12,11 @@ #include <linux/bitops.h> #endif
+#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
-#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
-/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00
diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 23dfe2e9e9..e47f40eac2 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -12,9 +12,11 @@ #include <linux/bitops.h> #endif
+#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
-#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
-/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00