Andes CPU supports cache and TLB ECC. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang ycliang@andestech.com --- arch/riscv/cpu/andesv5/cpu.c | 1 + arch/riscv/include/asm/arch-andes/csr.h | 3 +++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index c9288dcb51..c011c00a94 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -36,6 +36,7 @@ void harts_early_init(void) mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | \ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl |= MCACHE_CTL_IC_EN; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 755504c3c4..1a34618066 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -19,11 +19,14 @@
#define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_IC_ECCEN BIT(3) +#define MCACHE_CTL_DC_ECCEN BIT(5) #define MCACHE_CTL_CCTL_SUEN BIT(8) #define MCACHE_CTL_IC_PREFETCH_EN BIT(9) #define MCACHE_CTL_DC_PREFETCH_EN BIT(10) #define MCACHE_CTL_DC_WAROUND_EN BIT(13) #define MCACHE_CTL_L2C_WAROUND_EN BIT(15) +#define MCACHE_CTL_TLB_ECCEN BIT(18) #define MCACHE_CTL_DC_COHEN BIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20)