Hi Heiko,
On 17.2.2016 07:34, Heiko Schocher wrote:
Hello Michal,
Am 16.02.2016 um 17:04 schrieb Michal Simek:
Hi Heiko,
On 16.2.2016 14:32, Heiko Schocher wrote:
Hello Michal,
Am 16.02.2016 um 13:12 schrieb Michal Simek:
Hi Stephen,
trying to run the latest testing on zynq board and getting this main_signon error.
This is what I am running ./test/py/test.py --bd zynq_zc702 --build --board-identity zc702 and getting below.
Does this board has SPL support without SPL serial output?
I do load u-boot via jtag that's why SPL logs are not visible.
If so, can you try my patch: http://patchwork.ozlabs.org/patch/583348/
I have applied your patch but it is still not working.
If I run full flow with SPL then I can't see any issue.
I am not an expert of test/py (I still try to dig into it), but as I understand it, it looks if CONFIG_SPL is defined, if so, the framework expects a SPL output first, if not found, it raises the error you see ...
My patch fixes this, for boards which use SPL, but without serial SPL output ...
Now you test only u-boot with SPL configured with SPL serial output ...
I think Stephen can say here more, how to solve this ...
Ok. I have spent some time on this. Your patch is covering a little bit different case than I have. We have in general two used cases. One is to use SPL as first stage bootloader and then private full featured FSBL. Both of them works with the same u-boot image. It means I can build uboot with SPL and run two test sets. One with SPL which is working fine and the second without but there is no reason to rebuild u-boot without SPL just to pass testing. It means the feature I am looking for is more about ignoring SPL signon instead of supporting cases where SPL doesn't print anything.
Thanks, Michal