Initial support for Extreme Engineering Solutions XPedite5170 - a MPC8640-based 3U VPX single board computer with a PMC/XMC site.
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/xes/xpedite5170/Makefile | 52 +++ board/xes/xpedite5170/config.mk | 32 ++ board/xes/xpedite5170/ddr.c | 168 ++++++++ board/xes/xpedite5170/law.c | 52 +++ board/xes/xpedite5170/u-boot.lds | 132 ++++++ board/xes/xpedite5170/xpedite5170.c | 111 +++++ include/configs/XPEDITE5170.h | 758 +++++++++++++++++++++++++++++++++++ 10 files changed, 1310 insertions(+), 0 deletions(-) create mode 100644 board/xes/xpedite5170/Makefile create mode 100644 board/xes/xpedite5170/config.mk create mode 100644 board/xes/xpedite5170/ddr.c create mode 100644 board/xes/xpedite5170/law.c create mode 100644 board/xes/xpedite5170/u-boot.lds create mode 100644 board/xes/xpedite5170/xpedite5170.c create mode 100644 include/configs/XPEDITE5170.h
diff --git a/MAINTAINERS b/MAINTAINERS index bf076b9..5331e92 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -428,6 +428,7 @@ Rune Torgersen runet@innovsys.com
Peter Tyser ptyser@xes-inc.com
+ XPEDITE5170 MPC8640 XPEDITE5200 MPC8548 XPEDITE5370 MPC8572
diff --git a/MAKEALL b/MAKEALL index c98d03a..47b6bf4 100755 --- a/MAKEALL +++ b/MAKEALL @@ -407,6 +407,7 @@ LIST_86xx=" \ MPC8610HPCD \ MPC8641HPCN \ sbc8641d \ + XPEDITE5170 \ "
######################################################################### diff --git a/Makefile b/Makefile index 81a5cd0..a64d0e4 100644 --- a/Makefile +++ b/Makefile @@ -2558,6 +2558,9 @@ MPC8641HPCN_config: unconfig sbc8641d_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
+XPEDITE5170_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc86xx xpedite5170 xes + ######################################################################### ## 74xx/7xx Systems ######################################################################### diff --git a/board/xes/xpedite5170/Makefile b/board/xes/xpedite5170/Makefile new file mode 100644 index 0000000..fea6686 --- /dev/null +++ b/board/xes/xpedite5170/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/xes/xpedite5170/config.mk b/board/xes/xpedite5170/config.mk new file mode 100644 index 0000000..c3df6d5 --- /dev/null +++ b/board/xes/xpedite5170/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2009 Extreme Engineering Solutions, Inc. +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# XPedite5170 +# +TEXT_BASE = 0xfff00000 + +PLATFORM_RELFLAGS += -mrelocatable + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/xes/xpedite5170/ddr.c b/board/xes/xpedite5170/ddr.c new file mode 100644 index 0000000..1d57d09 --- /dev/null +++ b/board/xes/xpedite5170/ddr.c @@ -0,0 +1,168 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_bus_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) { + i2c_address = SPD_EEPROM_ADDRESS1; +#ifdef SPD_EEPROM_ADDRESS2 + } else if (ctrl_num == 1) { + i2c_address = SPD_EEPROM_ADDRESS2; +#endif + } else { + /* An inalid ctrl number was give, use default SPD */ + printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num); + i2c_address = SPD_EEPROM_ADDRESS1; + } + + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * PCB routing on the XPedite5170 is nearly identical to the XPedite5370 + * so we use the XPedite5370 settings as a basis for the XPedite5170. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = fsl_ddr_get_mem_data_rate() / 1000000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5170/law.c b/board/xes/xpedite5170/law.c new file mode 100644 index 0000000..0b7d9ef --- /dev/null +++ b/board/xes/xpedite5170/law.c @@ -0,0 +1,52 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE + /* NAND LAW covers 2 NAND flashes */ + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5170/u-boot.lds b/board/xes/xpedite5170/u-boot.lds new file mode 100644 index 0000000..b71a7d6 --- /dev/null +++ b/board/xes/xpedite5170/u-boot.lds @@ -0,0 +1,132 @@ +/* + * Copyright 2006, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c new file mode 100644 index 0000000..f4231a9 --- /dev/null +++ b/board/xes/xpedite5170/xpedite5170.c @@ -0,0 +1,111 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/io.h> +#include <fdt_support.h> +#include <pca953x.h> + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI) +extern void ft_board_pci_setup(void *blob, bd_t *bd); +#endif + +int checkboard(void) +{ + char *s; + + printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + return 0; +} +/* + * Print out which flash was booted from and if booting from the 2nd flash, + * swap flash chip selects to maintain consistent flash numbering/addresses. + */ +static void flash_cs_fixup(void) +{ + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + ccsr_lbc_t *lbc = &immap->im_lbc; + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); + out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + + out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); + out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h new file mode 100644 index 0000000..6445e3e --- /dev/null +++ b/include/configs/XPEDITE5170.h @@ -0,0 +1,758 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5170 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ +#define CONFIG_SYS_BOARD_NAME "XPedite5170" +#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_ALTIVEC 1 + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ + +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe0000000 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ + +/* + * L2CR setup + */ +#define CONFIG_SYS_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_DMA_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ +#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_JFFS2_NAND + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ + {0xf7f00000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ + OR_GPCM_CSNT |\ + OR_GPCM_XACS |\ + OR_GPCM_ACS_DIV2 |\ + OR_GPCM_SCY_8 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR |\ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ + OR_GPCM_BCTLD |\ + OR_GPCM_CSNT |\ + OR_GPCM_ACS_DIV4 |\ + OR_GPCM_SCY_4 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR) + +/* Optional NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - PEX8518 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - VPX P1 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * BAT mappings + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 1G PCI-Express 1 Memory + */ +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATU_BL_1G |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M PCI-Express 2 Memory + */ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATU_BL_512M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U + +/* + * BAT3 1M Cache-inhibited, guarded + * 0xe000_0000 1M CCSR + */ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + */ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATU_BL_32M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ + BATU_BL_128K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L +#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U + +/* + * BAT6 256M Cache-inhibited, guarded + * 0xf000_0000 256M FLASH + */ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ + BATU_BL_256M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U + +/* Map the last 1M of flash where we're running from reset */ +#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY + +/* + * BAT7 64M Cache-inhibited, guarded + * 0xe800_0000 64K NAND FLASH + * 0xe804_0000 128K DUART Registers + */ +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ + BATU_BL_512K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U + +/* + * Command configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_FSL_DMA /* Enable Freescale DMA engine */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* + * Flash memory map: + * fffc0000 - ffffffff Pri FDT (256KB) + * fff80000 - fffbffff Pri U-Boot Environment (256 KB) + * fff00000 - fff7ffff Pri U-Boot (512 KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7fc0000 - f7ffffff Sec FDT (256KB) + * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f7ffff Sec U-Boot (512 KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5170\0" \ + "fdtfile=/home/user/xpedite5170.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */