Re: [U-Boot] [PATCH] ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32

On 01/26/2018 17:28, Tom Rini wrote:

Now that we have and use wait_for_bit_le32() available, the callers of cm_write_with_phase() should not be casting values to u32 and instead we expect a const void *, so provide that directly.

Fixes: 48263504c8d5 ("wait_bit: use wait_for_bit_le32 and remove wait_for_bit") Cc: Marek Vasut marex@denx.de Signed-off-by: Tom Rini trini@konsulko.com

---

arch/arm/mach-socfpga/clock_manager_gen5.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 3d048ba3e432..4e5b6d169371 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -33,7 +33,7 @@ static void cm_write_ctrl(u32 val) }

/* function to write a clock register that has phase information */ -static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) +static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)

Shouldn't that better be a non-const void * since it is used for writing a value, too? That 'const' is later casted away by __arch_putl(), but it still looks wrong to me.

Simon

{ int ret;

@@ -268,26 +268,26 @@ int cm_basic_init(const struct cm_config * const cfg) * are aligned nicely; so we can change any phase. */ ret = cm_write_with_phase(cfg->ddrdqsclk,

•                             (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
  

•                             &clock_manager_base->sdr_pll.ddrdqsclk,
                              CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
    if (ret)
            return ret;
  
    /* SDRAM DDR2XDQSCLK */
    ret = cm_write_with_phase(cfg->ddr2xdqsclk,
  

•                             (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
  

•                             &clock_manager_base->sdr_pll.ddr2xdqsclk,
                              CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
    if (ret)
            return ret;
  
    ret = cm_write_with_phase(cfg->ddrdqclk,
  

•                             (u32)&clock_manager_base->sdr_pll.ddrdqclk,
  

•                             &clock_manager_base->sdr_pll.ddrdqclk,
                              CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
    if (ret)
            return ret;
  
    ret = cm_write_with_phase(cfg->s2fuser2clk,
  

•                             (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
  

•                             &clock_manager_base->sdr_pll.s2fuser2clk,
                              CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
    if (ret)
            return ret;
  

-- 2.7.4