On Monday, June 30, 2014 at 11:43:24 PM, Jörg Krause wrote:
On 06/30/2014 11:15 PM, Marek Vasut wrote:
On Monday, June 30, 2014 at 10:55:37 PM, Jörg Krause wrote: [...]
- You applied "allow multiple buffer allocs per ep"
Setting #define CONFIG_SYS_CACHELINE_SIZE 32 to my config file helped here. But still timeouts. First run almost always runs fine, only sometimes timeouts while receiving a packet, but always running to the end. Running tftp after this a second time and more fails with a ERROR: The remote end did not respond in time. at drivers/usb/gadget/ether.c:2388/usb_eth_init(), but sometimes it works.
Setting CONFIG_SYS_CACHELINE_SIZE 32 does not make it better (as I previously wrote it).
Sorry, this is a typo. It should be CONFIG_SYS_CACHELINE_SIZE 16 (not 32).
MX28 has 32b-long cachelines. Setting this to 16 is nonsense. [...]
Yes it is. But if I do not set cacheline size to 32 in my config header file it will be 64, as I stated in a previous mail.
I checked this and I found that ARCH_DMA_MINALIGN is set to 64, which is not true for Freescale i.MX28. This processor has an ARM926EJ-S, which has an cache line size of 32. In arch/arm/include/asm/cache.h the macro ARCH_DMA_MINALIGN is defined as followed: #ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #else #define ARCH_DMA_MINALIGN 64 #endif And in /arch/arm/cpu/arm926ejs/cache.c as followed: #ifndef CONFIG_SYS_CACHELINE_SIZE #define CONFIG_SYS_CACHELINE_SIZE 32 #endif arch/arm/include/asm/cache.h does not see the definition of CONFIG_SYS_CACHELINE_SIZE in /arch/arm/cpu/arm926ejs/cache.c, so it's a bad place to put it in there.I was just curious of the impact on the behaviour of the USB ethernet gadget driver.
Well okay, cacheline length and DMA alignment needs are two different things. Larger than necessary ARCH_DMA_MINALIGN cannot hurt, though there should be a patch adding CONFIG_SYS_CACHELINE_SIZE 32 for MXS into include/configs/mxs.h it seems.
Best regards, Marek Vasut