Used #Defined IDX values so as not to confuse those not familiar with the naming and ordering of the MDDRC config registers.
Signed-off-by: Martha M Stan mmarx@silicontkx.com --- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- cpu/mpc512x/fixed_sdram.c | 26 +++++++++++++++----------- include/asm-ppc/immap_512x.h | 6 ++++++ 3 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 13bd73c..a5be586 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -170,10 +170,10 @@ phys_size_t initdram(int board_type) * to the Default Micron ones for all but the earliest Rev 4 boards */ u32 elpida_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, };
u32 elpida_init_sequence[] = { diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61e..d92f738 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,13 @@ #include <asm/mpc512x.h>
/* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings in MEMORY order of the 4 MDDRC cfg registers */ -u32 default_mddrc_config[4] = { +u32 default_mddrc_regs[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ - CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ + CONFIG_SYS_MDDRC_TIME_CFG2 /* time_config2 */ };
u32 default_init_seq[] = { @@ -79,11 +79,12 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); + u32 *mddrc_regs; u32 i;
/* take default settings and init sequence if necessary */ if (mddrc_config == NULL) - mddrc_config = default_mddrc_config; + mddrc_regs = default_mddrc_regs; if (dram_init_seq == NULL) { dram_init_seq = default_init_seq; seq_sz = sizeof(default_init_seq)/sizeof(u32); @@ -130,18 +131,21 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + + out_be32(&im->mddrc.ddr_sys_config, mddrc_regs[MDDRC_SYS_CFG_IDX] + | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_regs[MDDRC_TIME_CFG0_IDX] + & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_regs[MDDRC_TIME_CFG1_IDX]); + out_be32(&im->mddrc.ddr_time_config2, mddrc_regs[MDDRC_TIME_CFG2_IDX]);
/* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
/* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_regs[MDDRC_TIME_CFG0_IDX]); + out_be32(&im->mddrc.ddr_sys_config, mddrc_regs[MDDRC_SYS_CFG_IDX]);
return msize; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 79cdd80..2294b78 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -346,6 +346,12 @@ typedef struct ddr512x { #define MDDRC_SYS_CFG_CMD_MASK 0x10000000 #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF
+/* MDDRC registers in memory order */ +#define MDDRC_SYS_CFG_IDX 0 +#define MDDRC_TIME_CFG0_IDX 1 +#define MDDRC_TIME_CFG1_IDX 2 +#define MDDRC_TIME_CFG2_IDX 3 + /* * DMA/Messaging Unit */