[U-Boot] [PATCH]: add canyonlands RAM-boot target

13 Mar 2011

This Patch adds another build target for the AMCC Canyonlands 
[PPC460Ex] eval board, this target can be used to do NAND flash or NOR 
flash programming in a virgin board using u-boot commands. Using JTAG 
debugger(e.g. BDI2000/3000) configured to setup the SDRAM.
     here are TLB entries required to load RAM-u-boot (for BDI2000/3000):
     WTLB   0x00000095  0x0000003F  ;SDRAM 256MB @ 0x00000000
     WTLB      0xE1000005  0x4E10001B
do SDRAM configuration.
Then do the following usin JTAG emulator:
     460EX>load 0x01000000 u-boot.bin bin
     460EX>go
Back to serial session that connected to canyonlands's serial port.
Signed-off-by: Fawaz Gaili fwazgai@gmail.com
  Cc: Stefan Roese sr@denx.de
  Cc: Wolfgang Denk wd@denx.de
  Cc: Felix Radensky felix@embedded-sol.com
---
  arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c         |   11 ++-
  arch/powerpc/cpu/ppc4xx/Makefile               |    2 +
  board/amcc/canyonlands/canyonlands.c           |    3 +-
  board/amcc/canyonlands/init.S                  |    6 ++
  board/amcc/canyonlands/u-boot-ram.lds          |   96 ++++++++++++++++++++
  boards.cfg                                     |    1 +
  include/configs/canyonlands.h                  |   31 +++++--
  7 files changed, 137 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c 
b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 95df1d9..2660cd2 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -66,7 +66,8 @@
                 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);    \
      } while (0)
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if (!defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT))    \
+    || defined(CONFIG_NAND_SPL)
  static void update_rdcc(void)
  {
      u32 val;
@@ -2896,7 +2897,8 @@ phys_size_t initdram(int board_type)
       * mustn't be reconfigured again since we're already running
       * from SDRAM.
       */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if (!defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT)) \
+    || defined(CONFIG_NAND_SPL)
      unsigned long val;
#if defined(CONFIG_440)
@@ -3013,12 +3015,13 @@ phys_size_t initdram(int board_type)
  #endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT)    \
+ && !defined(CONFIG_NAND_SPL)
      /*------------------------------------------------------------------
       | DQS calibration.
       +-----------------------------------------------------------------*/
      DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+#endif /* !defined(CONFIG_NAND_U_BOOT && CONFIG_SYS_RAMBOOT) && 
!defined(CONFIG_NAND_SPL) */
  #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
diff --git a/arch/powerpc/cpu/ppc4xx/Makefile 
b/arch/powerpc/cpu/ppc4xx/Makefile
index d97ca20..02a48f9 100644
--- a/arch/powerpc/cpu/ppc4xx/Makefile
+++ b/arch/powerpc/cpu/ppc4xx/Makefile
@@ -36,9 +36,11 @@ COBJS    := 40x_spd_sdram.o
ifndef CONFIG_NAND_SPL
  ifndef CONFIG_NAND_U_BOOT
+ifndef CONFIG_SYS_RAMBOOT
  COBJS    += 44x_spd_ddr.o
  endif
  endif
+endif
  COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
  COBJS-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
  COBJS    += 4xx_pci.o
diff --git a/board/amcc/canyonlands/canyonlands.c 
b/board/amcc/canyonlands/canyonlands.c
index 80e2739..d1f5e4f 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -390,8 +390,8 @@ int board_early_init_r (void)
       */
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-    mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) \
+    || defined(CONFIG_SYS_RAMBOOT)    mtebc(PB3CR, 
CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  #else
      mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  #endif
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 8b7bfce..526d8bd 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -66,6 +66,13 @@ tlbtab:
      tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, 
CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
  #endif
+#ifdef CONFIG_SYS_RAMBOOT
+#if CONFIG_SYS_MBYTES_SDRAM >= 512
+    tlbentry(0x10000000, SZ_256M, 0x10000000, 0x0, 
AC_R|AC_W|SA_G|SA_I|AC_X)
+    /*additional entry required*/
+#endif
+#endif
+
      tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
      tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | 
SA_IG)
      tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW 
| SA_IG)
diff --git a/board/amcc/canyonlands/u-boot-ram.lds 
b/board/amcc/canyonlands/u-boot-ram.lds
new file mode 100644
index 0000000..e98d947
--- /dev/null
+++ b/board/amcc/canyonlands/u-boot-ram.lds
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2011
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * Fawaz Giali, Nile Center for Technology Research, fwazgai@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    arch/powerpc/cpu/ppc4xx/start.o    (.text*)
+    board/amcc/canyonlands/init.o        (.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/boards.cfg b/boards.cfg
index c3b164e..1f7f4dd 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -647,6 +647,7 @@ bluestone                    powerpc     ppc4xx      
-                   amcc
  bubinga                      powerpc     ppc4xx      
-                   amcc
  canyonlands                  powerpc     ppc4xx      
canyonlands         amcc           -           canyonlands:CANYONLANDS
  canyonlands_nand             powerpc     ppc4xx      
canyonlands         amcc           -           
canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+canyonlands_ramboot             powerpc     ppc4xx        
  canyonlands         amcc            -            
canyonlands:CANYONLANDS,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds
  ebony                        powerpc     ppc4xx      
-                   amcc
  glacier                      powerpc     ppc4xx      
canyonlands         amcc           -           canyonlands:GLACIER
  glacier_nand                 powerpc     ppc4xx      
canyonlands         amcc           -           
canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 8c03582..c7c817f 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -137,17 +137,31 @@
   * Environment
   *----------------------------------------------------------------------*/
  /*
- * Define here the location of the environment variables (FLASH).
+  * Define here the location of the environment variables (FLASH).
+  */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#define CONFIG_ENV_IS_IN_NAND   1   /* use NAND for environ vars */
+#define CONFIG_ENV_IS_EMBEDDED    1    /* use embedded environment */
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE        /* Store env in memory only*/
+#define CONFIG_ENV_SIZE            (8 << 10)
+/*
+ * In RAM-booting version, we have no environment storage. So we need to
+ * provide at least preliminary MAC addresses for the 4xx EMAC driver to
+ * register the interfaces.
   */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define    CONFIG_ETHADDR            4a:56:49:22:3e:43
+#define    CONFIG_ETH1ADDR            02:93:53:d5:06:98
+#else
  #define    CONFIG_ENV_IS_IN_FLASH    1    /* use FLASH for environment 
vars */
  #define CONFIG_SYS_NOR_CS        0    /* NOR chip connected to CSx */
  #define CONFIG_SYS_NAND_CS        3    /* NAND chip connected to CSx */
-#else
-#define    CONFIG_ENV_IS_IN_NAND    1    /* use NAND for environment 
vars  */
+#endif/*CONFIG_NAND_U_BOOT || CONFIG_NAND_SPL*/
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) \
+    || defined(CONFIG_SYS_RAMBOOT)
  #define CONFIG_SYS_NOR_CS        3    /* NOR chip connected to CSx */
  #define CONFIG_SYS_NAND_CS        0    /* NAND chip connected to CSx */
-#define CONFIG_ENV_IS_EMBEDDED    1    /* use embedded environment */
  #endif
/*
@@ -251,7 +265,7 @@
  /*------------------------------------------------------------------------------
   * DDR SDRAM
*----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
  #if !defined(CONFIG_ARCHES)
  /*
   * NAND booting U-Boot version uses a fixed initialization, since the 
whole
@@ -324,7 +338,7 @@
  #define CONFIG_SYS_SDRAM0_MMODE        0x00000432
  #define CONFIG_SYS_SDRAM0_MEMODE    0x00000004
  #endif    /* !defined(CONFIG_ARCHES) */
-#endif    /* !defined(CONFIG_NAND_U_BOOT) */
+#endif    /* !defined(CONFIG_NAND_U_BOOT) && 
!defined(CONFIG_SYS_RAMBOOT) */
#define CONFIG_SYS_MBYTES_SDRAM    512    /* 512MB            */
@@ -571,7 +585,8 @@
   * 0xfe00.0000 -> 4.ce00.0000
   */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)    \
+    || defined(CONFIG_SYS_RAMBOOT)
  /* Memory Bank 3 (NOR-FLASH) initialization                    */
  #define CONFIG_SYS_EBC_PB3AP        0x10055e00
  #define CONFIG_SYS_EBC_PB3CR        (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-- 
Best Regards
Fawaz Gaili
NCTR
NTC - Tower 8th floor


    