Hi Green,
From: Green Wan [mailto:green.wan@sifive.com] Sent: Tuesday, April 13, 2021 5:32 PM Cc: Green Wan; Sean Anderson; Bin Meng; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; open list Subject: [RFC PATCH v5 2/2] board: sifive: unmatched: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_si...
Signed-off-by: Green Wan green.wan@sifive.com Reviewed-by: Sean Anderson seanga2@gmail.com Reviewed-by: Bin Meng bmeng.cn@gmail.com
board/sifive/unmatched/spl.c | 15 +++++++++++++++
Is this CSR depends on unmatched board ? I just wonder why not add in /arch/riscv/cpu/ and create fu74, just like /arch/riscv/cpu/fu540/spl.c ?
Thanks, Rick
1 file changed, 15 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c index 5e1333b09a..ed48dac511 100644 --- a/board/sifive/unmatched/spl.c +++ b/board/sifive/unmatched/spl.c @@ -12,6 +12,7 @@ #include <log.h> #include <linux/delay.h> #include <linux/io.h> +#include <asm/csr.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/spl.h> @@ -22,6 +23,20 @@ #define MODE_SELECT_SD 0xb #define MODE_SELECT_MASK GENMASK(3, 0)
+#define CSR_U74_FEATURE_DISABLE 0x7c1
+void harts_early_init(void) +{
/** Feature Disable CSR** Clear feature disable CSR to '0' to turn on all features for* each core. This operation must be in M-mode.*/if (CONFIG_IS_ENABLED(RISCV_MMODE))csr_write(CSR_U74_FEATURE_DISABLE, 0);+}
int spl_board_init_f(void) { int ret; -- 2.31.0