Hi Pali,
On 8/31/2022 8:04 PM, Pali Rohár wrote:
PING????
Please cc me for freescale ppc boards. The patches not show in my patchwork[freenix].
I will put your patches into CI now.
Thanks, Peng.
On Sunday 21 August 2022 12:30:04 Pali Rohár wrote:
PING???? I have not received any response for these patches. Why you are ignoring me?
You have already merged commit "board: freescale: p1_p2_rdb_pc: Implement board_reset()" from v1 of this patch series https://source.denx.de/u-boot/u-boot/-/commit/20fb58fc5a1c83ee0085b2e9f7ecda... without applying reset workaround commit from v1 (also available in v2) which effectively broke reset support in U-Boot.
Why you are continuing breaking P1/P2 boards? >> Patches for this are already waiting on the list.
On Monday 01 August 2022 15:31:43 Pali Rohár wrote:
CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB.
With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board.
Signed-off-by: Pali Rohár pali@kernel.org
Changes in v2:
- Resend patch
- Update comment about watchdog
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- /*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared* after flipping it. If this register is set to one then CPLD triggers* reset of CPU in few ms.** CPLD does not trigger reset of CPU for 100ms after the last reset.** This means that trying to reset board via CPLD system reset register* cause reboot loop. To prevent this reboot loop, the only workaround* is to try to clear CPLD's system reset register as early as possible* and it has to be done in 100ms since the last start of reset.*/diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds* reboot loop due to broken CPLD state machine for reset line.*/board_early_init_f();
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1