From: Dinh Nguyen dinguyen@opensource.altera.com
Add SDRAM initialization for the SOCFPGA platform.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/sdram.c | 1311 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/sdram.h | 434 ++++++++++ include/configs/socfpga_cyclone5.h | 1 + 4 files changed, 1747 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/sdram.c create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 8b6e108..9bd649d 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,5 +9,5 @@
obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o + fpga_manager.o sdram.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/sdram.c b/arch/arm/cpu/armv7/socfpga/sdram.c new file mode 100644 index 0000000..88e7c58 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/sdram.c @@ -0,0 +1,1311 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <div64.h> +#include <watchdog.h> +#include <asm/arch/fpga_manager.h> +#include <asm/arch/sdram.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> + +#define COMPARE_FAIL_ACTION return 1; + +#define ADDRORDER2_INFO \ + "INFO: Changing address order to 2 (row, chip, bank, column)\n" +#define ADDRORDER0_INFO \ + "INFO: Changing address order to 0 (chip, row, bank, column)\n" + +/* define constant for 4G memory - used for SDRAM errata workaround */ +#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* Below function only applicable for SPL */ +static int compute_errata_rows(unsigned long long memsize, int cs, int width, + int rows, int banks, int cols) +{ + unsigned long long newrows; + int inewrowslog2; + int bits; + + debug("workaround rows - memsize %lld\n", memsize); + debug("workaround rows - cs %d\n", cs); + debug("workaround rows - width %d\n", width); + debug("workaround rows - rows %d\n", rows); + debug("workaround rows - banks %d\n", banks); + debug("workaround rows - cols %d\n", cols); + + newrows = lldiv(memsize, (cs * (width / 8))); + debug("rows workaround - term1 %lld\n", newrows); + + newrows = lldiv(newrows, ((1 << banks) * (1 << cols))); + debug("rows workaround - term2 %lld\n", newrows); + + /* Compute the hamming weight - same as number of bits set. + * Need to see if result is ordinal power of 2 before + * attempting log2 of result. + */ + bits = hweight32(newrows); + + debug("rows workaround - bits %d\n", bits); + + if (bits != 1) { + printf("SDRAM workaround failed, bits set %d\n", bits); + return rows; + } + + if (newrows > UINT_MAX) { + printf("SDRAM workaround rangecheck failed, %lld\n", newrows); + return rows; + } + + inewrowslog2 = __ilog2((unsigned int)newrows); + + debug("rows workaround - ilog2 %d, %d\n", inewrowslog2, + (int)newrows); + + if (inewrowslog2 == -1) { + printf("SDRAM workaround failed, newrows %d\n", (int)newrows); + return rows; + } + + return inewrowslog2; +} + +typedef struct _sdram_prot_rule { + uint32_t rule; /* SDRAM protection rule number: 0-19 */ + uint64_t sdram_start; /* SDRAM start address */ + uint64_t sdram_end; /* SDRAM end address */ + int valid; /* Rule valid or not? 1 - valid, 0 not*/ + + uint32_t security; + uint32_t portmask; + uint32_t result; + uint32_t lo_prot_id; + uint32_t hi_prot_id; +} sdram_prot_rule, *psdram_prot_rule; + +/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ + +static void sdram_set_rule(psdram_prot_rule prule) +{ + int regoffs; + uint32_t lo_addr_bits; + uint32_t hi_addr_bits; + int ruleno = prule->rule; + + /* Select the rule */ + regoffs = SDR_CTRLGRP_PROTRULERDWR_ADDRESS; + writel(ruleno, (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* Obtain the address bits */ + lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF); + hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF); + + debug("sdram set rule start %x, %lld\n", lo_addr_bits, + prule->sdram_start); + debug("sdram set rule end %x, %lld\n", hi_addr_bits, + prule->sdram_end); + + /* Set rule addresses */ + regoffs = SDR_CTRLGRP_PROTRULEADDR_ADDRESS; + writel(lo_addr_bits | (hi_addr_bits << 12), + (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* Set rule protection ids */ + regoffs = SDR_CTRLGRP_PROTRULEID_ADDRESS; + writel(prule->lo_prot_id | (prule->hi_prot_id << 12), + (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* Set the rule data */ + regoffs = SDR_CTRLGRP_PROTRULEDATA_ADDRESS; + writel(prule->security | (prule->valid << 2) | + (prule->portmask << 3) | (prule->result << 13), + (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* write the rule */ + regoffs = SDR_CTRLGRP_PROTRULERDWR_ADDRESS; + writel(ruleno | (1L << 5), + (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* Set rule number to 0 by default */ + writel(0, (SOCFPGA_SDR_ADDRESS + regoffs)); +} + +static void sdram_get_rule(psdram_prot_rule prule) +{ + int regoffs; + uint32_t protruleaddr; + uint32_t protruleid; + uint32_t protruledata; + int ruleno = prule->rule; + + /* Read the rule */ + regoffs = SDR_CTRLGRP_PROTRULERDWR_ADDRESS; + writel(ruleno, (SOCFPGA_SDR_ADDRESS + regoffs)); + writel(ruleno | (1L << 6), + (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* Get the addresses */ + regoffs = SDR_CTRLGRP_PROTRULEADDR_ADDRESS; + protruleaddr = readl(SOCFPGA_SDR_ADDRESS + regoffs); + prule->sdram_start = (protruleaddr & 0xFFF) << 20; + prule->sdram_end = ((protruleaddr >> 12) & 0xFFF) << 20; + + /* Get the configured protection IDs */ + regoffs = SDR_CTRLGRP_PROTRULEID_ADDRESS; + protruleid = readl(SOCFPGA_SDR_ADDRESS + regoffs); + prule->lo_prot_id = protruleid & 0xFFF; + prule->hi_prot_id = (protruleid >> 12) & 0xFFF; + + /* Get protection data */ + regoffs = SDR_CTRLGRP_PROTRULEDATA_ADDRESS; + protruledata = readl(SOCFPGA_SDR_ADDRESS + regoffs); + + prule->security = protruledata & 0x3; + prule->valid = (protruledata >> 2) & 0x1; + prule->portmask = (protruledata >> 3) & 0x3FF; + prule->result = (protruledata >> 13) & 0x1; +} + +static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end) +{ + sdram_prot_rule rule; + int rules; + int regoffs = SDR_CTRLGRP_PROTPORTDEFAULT_ADDRESS; + + /* Start with accepting all SDRAM transaction */ + writel(0x0, (SOCFPGA_SDR_ADDRESS + regoffs)); + + /* Clear all protection rules for warm boot case */ + + rule.sdram_start = 0; + rule.sdram_end = 0; + rule.lo_prot_id = 0; + rule.hi_prot_id = 0; + rule.portmask = 0; + rule.security = 0; + rule.result = 0; + rule.valid = 0; + rule.rule = 0; + + for (rules = 0; rules < 20; rules++) { + rule.rule = rules; + sdram_set_rule(&rule); + } + + /* new rule: accept SDRAM */ + rule.sdram_start = sdram_start; + rule.sdram_end = sdram_end; + rule.lo_prot_id = 0x0; + rule.hi_prot_id = 0xFFF; + rule.portmask = 0x3FF; + rule.security = 0x3; + rule.result = 0; + rule.valid = 1; + rule.rule = 0; + + /* set new rule */ + sdram_set_rule(&rule); + + /* default rule: reject everything */ + writel(0x3ff, (SOCFPGA_SDR_ADDRESS + regoffs)); +} + +static void sdram_dump_protection_config(void) +{ + sdram_prot_rule rule; + int rules; + int regoffs = SDR_CTRLGRP_PROTPORTDEFAULT_ADDRESS; + + debug("SDRAM Prot rule, default %x\n", + readl(SOCFPGA_SDR_ADDRESS + regoffs)); + + for (rules = 0; rules < 20; rules++) { + sdram_get_rule(&rule); + debug("Rule %d, rules ...\n", rules); + debug(" sdram start %llx\n", rule.sdram_start); + debug(" sdram end %llx\n", rule.sdram_end); + debug(" low prot id %d, hi prot id %d\n", + rule.lo_prot_id, + rule.hi_prot_id); + debug(" portmask %x\n", rule.portmask); + debug(" security %d\n", rule.security); + debug(" result %d\n", rule.result); + debug(" valid %d\n", rule.valid); + } +} + +/* Function to update the field within variable */ +static unsigned sdram_write_register_field(unsigned masked_value, + unsigned data, unsigned shift, unsigned mask) +{ + masked_value &= ~(mask); + masked_value |= (data << shift) & mask; + return masked_value; +} + +/* Function to write to register and verify the write */ +static unsigned sdram_write_verify(unsigned register_offset, unsigned reg_value) +{ +#ifndef SDRAM_MMR_SKIP_VERIFY + unsigned reg_value1; +#endif + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (SOCFPGA_SDR_ADDRESS+register_offset), reg_value); + /* Write to register */ + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); +#ifndef SDRAM_MMR_SKIP_VERIFY + debug(" Read and verify..."); + /* Read back the wrote value */ + reg_value1 = readl(SOCFPGA_SDR_ADDRESS + register_offset); + /* Indicate failure if value not matched */ + if (reg_value1 != reg_value) { + debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n", + (SOCFPGA_SDR_ADDRESS+register_offset), + reg_value, reg_value1); + return 1; + } + debug("correct!\n"); +#endif /* SDRAM_MMR_SKIP_VERIFY */ + return 0; +} + +/* Function to initialize SDRAM MMR */ +unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) +{ + unsigned long register_offset, reg_value; + unsigned long status = 0; + int addrorder; + char *paddrorderinfo = NULL; + +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) + + int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; + int width = 8; + int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; + int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS; + int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS; + unsigned long long workaround_memsize = MEMSIZE_4G; + + writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS, + &sysmgr_regs->iswgrp_handoff[4]); +#endif + + /***** CTRLCFG *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS) + debug("\nConfiguring CTRLCFG\n"); + register_offset = SDR_CTRLGRP_CTRLCFG_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE, + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB, + SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL, + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB, + SDR_CTRLGRP_CTRLCFG_MEMBL_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER + + /* SDRAM Failure When Accessing Non-Existent Memory + * Set the addrorder field of the SDRAM control register + * based on the CSBITs setting. + */ + + switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) { + case 1: + addrorder = 0; /* chip, row, bank, column */ + if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0) + paddrorderinfo = ADDRORDER0_INFO; + break; + case 2: + addrorder = 2; /* row, chip, bank, column */ + if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2) + paddrorderinfo = ADDRORDER2_INFO; + break; + default: + addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER; + break; + } + if (paddrorderinfo) + printf(paddrorderinfo); + + reg_value = sdram_write_register_field(reg_value, + addrorder, + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB, + SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN, + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB, + SDR_CTRLGRP_CTRLCFG_ECCEN_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN, + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB, + SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN, + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB, + SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT, + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB, + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN, + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB, + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS, + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB, + SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** DRAMTIMING1 *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC) + debug("Configuring DRAMTIMING1\n"); + register_offset = SDR_CTRLGRP_DRAMTIMING1_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL, + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB, + SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL, + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB, + SDR_CTRLGRP_DRAMTIMING1_TAL_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL, + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB, + SDR_CTRLGRP_DRAMTIMING1_TCL_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD, + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB, + SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW, + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB, + SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC, + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB, + SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** DRAMTIMING2 *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR) + debug("Configuring DRAMTIMING2\n"); + register_offset = SDR_CTRLGRP_DRAMTIMING2_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI, + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB, + SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD, + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB, + SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP, + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB, + SDR_CTRLGRP_DRAMTIMING2_TRP_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR, + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB, + SDR_CTRLGRP_DRAMTIMING2_TWR_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR, + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB, + SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** DRAMTIMING3 *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD) + debug("Configuring DRAMTIMING3\n"); + register_offset = SDR_CTRLGRP_DRAMTIMING3_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP, + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB, + SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS, + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB, + SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC, + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB, + SDR_CTRLGRP_DRAMTIMING3_TRC_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD, + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB, + SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD, + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB, + SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** DRAMTIMING4 *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT) + debug("Configuring DRAMTIMING4\n"); + register_offset = SDR_CTRLGRP_DRAMTIMING4_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT, + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB, + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT, + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB, + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** LOWPWRTIMING *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES) + debug("Configuring LOWPWRTIMING\n"); + register_offset = SDR_CTRLGRP_LOWPWRTIMING_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES, + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB, + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES, + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB, + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + /***** DRAMADDRW *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) + debug("Configuring DRAMADDRW\n"); + register_offset = SDR_CTRLGRP_DRAMADDRW_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS, + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB, + SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS + /* SDRAM Failure When Accessing Non-Existent Memory + * Update Preloader to artificially increase the number of rows so + * that the memory thinks it has 4GB of RAM. + */ + rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks, + cols); + + reg_value = sdram_write_register_field(reg_value, + rows, + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB, + SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS, + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB, + SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS + /* SDRAM Failure When Accessing Non-Existent Memory + * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to + * log2(number of chip select bits). Since there's only + * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, + * which is the same as "chip selects" - 1. + */ + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1, + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB, + SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + /***** DRAMIFWIDTH *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH + debug("Configuring DRAMIFWIDTH\n"); + register_offset = SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH, + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB, + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** DRAMDEVWIDTH *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH + debug("Configuring DRAMDEVWIDTH\n"); + register_offset = SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH, + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB, + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** LOWPWREQ *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK + debug("Configuring LOWPWREQ\n"); + register_offset = SDR_CTRLGRP_LOWPWREQ_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK, + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB, + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** DRAMINTR *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN + debug("Configuring DRAMINTR\n"); + register_offset = SDR_CTRLGRP_DRAMINTR_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN, + SDR_CTRLGRP_DRAMINTR_INTREN_LSB, + SDR_CTRLGRP_DRAMINTR_INTREN_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** STATICCFG *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA) + debug("Configuring STATICCFG\n"); + register_offset = SDR_CTRLGRP_STATICCFG_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL, + SDR_CTRLGRP_STATICCFG_MEMBL_LSB, + SDR_CTRLGRP_STATICCFG_MEMBL_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA, + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB, + SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** CTRLWIDTH *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH + debug("Configuring CTRLWIDTH\n"); + register_offset = SDR_CTRLGRP_CTRLWIDTH_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH, + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB, + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** PORTCFG *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN + debug("Configuring PORTCFG\n"); + register_offset = SDR_CTRLGRP_PORTCFG_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN, + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB, + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** FIFOCFG *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC) + debug("Configuring FIFOCFG\n"); + register_offset = SDR_CTRLGRP_FIFOCFG_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE, + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB, + SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC, + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB, + SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPPRIORITY *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY + debug("Configuring MPPRIORITY\n"); + register_offset = SDR_CTRLGRP_MPPRIORITY_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY, + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB, + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPWEIGHT_MPWEIGHT_0 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 + debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); + register_offset = SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPWEIGHT_MPWEIGHT_1 *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0) + debug("Configuring MPWEIGHT_MPWEIGHT_1\n"); + register_offset = SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPWEIGHT_MPWEIGHT_2 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 + debug("Configuring MPWEIGHT_MPWEIGHT_2\n"); + register_offset = SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPWEIGHT_MPWEIGHT_3 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 + debug("Configuring MPWEIGHT_MPWEIGHT_3\n"); + register_offset = SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB, + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPPACING_MPPACING_0 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 + debug("Configuring MPPACING_MPPACING_0\n"); + register_offset = SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0, + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB, + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + /***** MPPACING_MPPACING_1 *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0) + debug("Configuring MPPACING_MPPACING_1\n"); + register_offset = SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32, + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB, + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0, + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB, + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + /***** MPPACING_MPPACING_2 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 + debug("Configuring MPPACING_MPPACING_2\n"); + register_offset = SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4, + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB, + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPPACING_MPPACING_3 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 + debug("Configuring MPPACING_MPPACING_3\n"); + register_offset = SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36, + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB, + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPTHRESHOLDRST_MPTHRESHOLDRST_0 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); + register_offset = SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0, + SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB, +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPTHRESHOLDRST_MPTHRESHOLDRST_1 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_1\n"); + register_offset = SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32, +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB, +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + + /***** MPTHRESHOLDRST_MPTHRESHOLDRST_2 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_2\n"); + register_offset = SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64, +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB, +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK); + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + /***** PHYCTRL_PHYCTRL_0 *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 + debug("Configuring PHYCTRL_PHYCTRL_0\n"); + register_offset = SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS; + /* Read original register value */ + reg_value = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0; + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + +/* newly added registers */ + /***** CPORTWIDTH_CPORTWIDTH *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH + debug("Configuring CPORTWIDTH\n"); + register_offset = SDR_CTRLGRP_CPORTWIDTH_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH, + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB, + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); +#endif + + /***** CPORTWMAP_CPORTWMAP *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP + debug("Configuring CPORTWMAP\n"); + register_offset = SDR_CTRLGRP_CPORTWMAP_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP, + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB, + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); +#endif + + /***** CPORTRMAP_CPORTRMAP *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP + debug("Configuring CPORTRMAP\n"); + register_offset = SDR_CTRLGRP_CPORTRMAP_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP, + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB, + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); +#endif + + /***** RFIFOCMAP_RFIFOCMAP *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP + debug("Configuring RFIFOCMAP\n"); + register_offset = SDR_CTRLGRP_RFIFOCMAP_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP, + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB, + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); +#endif + + /***** WFIFOCMAP_WFIFOCMAP *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP + debug("Configuring WFIFOCMAP\n"); + register_offset = SDR_CTRLGRP_WFIFOCMAP_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP, + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB, + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); +#endif + + /***** CPORTRDWR_CPORTRDWR *****/ +#ifdef CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR + debug("Configuring CPORTRDWR\n"); + register_offset = SDR_CTRLGRP_CPORTRDWR_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR, + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB, + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); +#endif +/* end of newly added registers */ + + + /***** DRAMODT *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ) || \ +defined(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE) + debug("Configuring DRAMODT\n"); + register_offset = SDR_CTRLGRP_DRAMODT_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ, + SDR_CTRLGRP_DRAMODT_READ_LSB, + SDR_CTRLGRP_DRAMODT_READ_MASK); +#endif +#ifdef CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE + reg_value = sdram_write_register_field(reg_value, + CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE, + SDR_CTRLGRP_DRAMODT_WRITE_LSB, + SDR_CTRLGRP_DRAMODT_WRITE_MASK); +#endif + if (sdram_write_verify(register_offset, reg_value) == 1) { + status = 1; + COMPARE_FAIL_ACTION + } +#endif + + /***** FPGAPORTRST *****/ +#if defined(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED) + debug("Configuring FPGAPORTRST\n"); + register_offset = SDR_CTRLGRP_FPGAPORTRST_ADDRESS; + /* All value will be provided */ + reg_value = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST; + + /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ + writel(reg_value, &sysmgr_regs->iswgrp_handoff[3]); + + /* only enable if the FPGA is programmed */ + if (fpgamgr_test_fpga_ready()) { + if (sdram_write_verify(register_offset, reg_value) == 1) { + /* Set status to 1 to ensure we return failed status + if user wish the COMPARE_FAIL_ACTION not to do anything. + This is to cater scenario where user wish to + continue initlization even verify failed. */ + status = 1; + COMPARE_FAIL_ACTION + } + } +#endif + + /* Restore the SDR PHY Register if valid */ + if (sdr_phy_reg != 0xffffffff) + writel(sdr_phy_reg, SOCFPGA_SDR_ADDRESS + + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS); + +/***** Final step - apply configuration changes *****/ + debug("Configuring STATICCFG_\n"); + register_offset = SDR_CTRLGRP_STATICCFG_ADDRESS; + /* Read original register value */ + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + reg_value = sdram_write_register_field(reg_value, 1, + SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB, + SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK); + debug(" Write - Address "); + debug("0x%08x Data 0x%08x\n", + (unsigned)(SOCFPGA_SDR_ADDRESS+register_offset), + (unsigned)reg_value); + writel(reg_value, (SOCFPGA_SDR_ADDRESS + register_offset)); + reg_value = readl(SOCFPGA_SDR_ADDRESS + register_offset); + debug(" Read value without verify 0x%08x\n", (unsigned)reg_value); + + sdram_set_protection_config(0, sdram_calculate_size()); + + sdram_dump_protection_config(); + + return status; +} + +unsigned sdram_calibration_full(void) +{ + return sdram_calibration(); +} + +/* To calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + * + * NOTE!!!! + * This function is compiled and linked into the preloader and + * Uboot (there may be others). So if this function changes, the Preloader + * and UBoot must be updated simultaneously. + */ +unsigned long sdram_calculate_size(void) +{ + unsigned long temp; + unsigned long row, bank, col, cs, width; + + temp = readl(SOCFPGA_SDR_ADDRESS + + SDR_CTRLGRP_DRAMADDRW_ADDRESS); + col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; + + /* SDRAM Failure When Accessing Non-Existent Memory + * Use ROWBITS from Quartus/QSys to calculate SDRAM size + * since the FB specifies we modify ROWBITs to work around SDRAM + * controller issue. + * + * If the stored handoff value for rows is 0, it probably means + * the preloader is older than UBoot. Use the + * #define from the SOCEDS Tools per Crucible review + * uboot-socfpga-204. Note that this is not a supported + * configuration and is not tested. The customer + * should be using preloader and uboot built from the + * same tag. + */ + row = readl(&sysmgr_regs->iswgrp_handoff[4]); + if (row == 0) + row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; + /* If the stored handoff value for rows is greater than + * the field width in the sdr.dramaddrw register then + * something is very wrong. Revert to using the the #define + * value handed off by the SOCEDS tool chain instead of + * using a broken value. + */ + if (row > 31) + row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; + + bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; + + /* SDRAM Failure When Accessing Non-Existent Memory + * Use CSBITs from Quartus/QSys to calculate SDRAM size + * since the FB specifies we modify CSBITs to work around SDRAM + * controller issue. + */ + cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB; + cs += 1; + + cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; + + width = readl(SOCFPGA_SDR_ADDRESS + + SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS); + /* ECC would not be calculated as its not addressible */ + if (width == SDRAM_WIDTH_32BIT_WITH_ECC) + width = 32; + if (width == SDRAM_WIDTH_16BIT_WITH_ECC) + width = 16; + + /* calculate the SDRAM size base on this info */ + temp = 1 << (row + bank + col); + temp = temp * cs * (width / 8); + + debug("sdram_calculate_memory returns %ld\n", temp); + + return temp; +} diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h new file mode 100644 index 0000000..b6d971e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/sdram.h @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SDRAM_H_ +#define _SDRAM_H_ + +#ifndef __ASSEMBLY__ + +/* function declaration */ +unsigned long sdram_calculate_size(void); +unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg); +unsigned sdram_calibration_full(void); + +extern int sdram_calibration(void); + +/* Group: sdr.phygrp.sccgrp */ +#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0 +/* Group: sdr.phygrp.phymgrgrp */ +#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000 +/* Group: sdr.phygrp.rwmgrgrp */ +#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000 +/* Group: sdr.phygrp.datamgrgrp */ +#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000 +/* Group: sdr.phygrp.regfilegrp */ +#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800 +/* Group: sdr.ctrlgrp */ +#define SDR_CTRLGRP_ADDRESS 0x5000 +/* Register: sdr.ctrlgrp.ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000 +/* Register: sdr.ctrlgrp.dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004 +/* Register: sdr.ctrlgrp.dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008 +/* Register: sdr.ctrlgrp.dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c +/* Register: sdr.ctrlgrp.dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010 +/* Register: sdr.ctrlgrp.lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014 +/* Register: sdr.ctrlgrp.dramodt */ +#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018 +/* Register: sdr.ctrlgrp.dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c +/* Register: sdr.ctrlgrp.dramifwidth */ +#define SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS 0x5030 +/* Register: sdr.ctrlgrp.dramdevwidth */ +#define SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS 0x5034 +/* Register: sdr.ctrlgrp.dramsts */ +#define SDR_CTRLGRP_DRAMSTS_ADDRESS 0x5038 +/* Register: sdr.ctrlgrp.dramintr */ +#define SDR_CTRLGRP_DRAMINTR_ADDRESS 0x503c +/* Register: sdr.ctrlgrp.sbecount */ +#define SDR_CTRLGRP_SBECOUNT_ADDRESS 0x5040 +/* Register: sdr.ctrlgrp.dbecount */ +#define SDR_CTRLGRP_DBECOUNT_ADDRESS 0x5044 +/* Register: sdr.ctrlgrp.erraddr */ +#define SDR_CTRLGRP_ERRADDR_ADDRESS 0x5048 +/* Register: sdr.ctrlgrp.dropcount */ +#define SDR_CTRLGRP_DROPCOUNT_ADDRESS 0x504c +/* Register: sdr.ctrlgrp.dropaddr */ +#define SDR_CTRLGRP_DROPADDR_ADDRESS 0x5050 +/* Register: sdr.ctrlgrp.lowpwreq */ +#define SDR_CTRLGRP_LOWPWREQ_ADDRESS 0x5054 +/* Register: sdr.ctrlgrp.lowpwrack */ +#define SDR_CTRLGRP_LOWPWRACK_ADDRESS 0x5058 +/* Register: sdr.ctrlgrp.staticcfg */ +#define SDR_CTRLGRP_STATICCFG_ADDRESS 0x505c +/* Register: sdr.ctrlgrp.ctrlwidth */ +#define SDR_CTRLGRP_CTRLWIDTH_ADDRESS 0x5060 +/* Register: sdr.ctrlgrp.cportwidth */ +#define SDR_CTRLGRP_CPORTWIDTH_ADDRESS 0x5064 +/* Register: sdr.ctrlgrp.cportwmap */ +#define SDR_CTRLGRP_CPORTWMAP_ADDRESS 0x5068 +/* Register: sdr.ctrlgrp.cportrmap */ +#define SDR_CTRLGRP_CPORTRMAP_ADDRESS 0x506c +/* Register: sdr.ctrlgrp.rfifocmap */ +#define SDR_CTRLGRP_RFIFOCMAP_ADDRESS 0x5070 +/* Register: sdr.ctrlgrp.wfifocmap */ +#define SDR_CTRLGRP_WFIFOCMAP_ADDRESS 0x5074 +/* Register: sdr.ctrlgrp.cportrdwr */ +#define SDR_CTRLGRP_CPORTRDWR_ADDRESS 0x5078 +/* Register: sdr.ctrlgrp.portcfg */ +#define SDR_CTRLGRP_PORTCFG_ADDRESS 0x507c +/* Register: sdr.ctrlgrp.fpgaportrst */ +#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 +/* Register: sdr.ctrlgrp.fifocfg */ +#define SDR_CTRLGRP_FIFOCFG_ADDRESS 0x5088 +/* Register: sdr.ctrlgrp.protportdefault */ +#define SDR_CTRLGRP_PROTPORTDEFAULT_ADDRESS 0x508c +/* Register: sdr.ctrlgrp.protruleaddr */ +#define SDR_CTRLGRP_PROTRULEADDR_ADDRESS 0x5090 +/* Register: sdr.ctrlgrp.protruleid */ +#define SDR_CTRLGRP_PROTRULEID_ADDRESS 0x5094 +/* Register: sdr.ctrlgrp.protruledata */ +#define SDR_CTRLGRP_PROTRULEDATA_ADDRESS 0x5098 +/* Register: sdr.ctrlgrp.protrulerdwr */ +#define SDR_CTRLGRP_PROTRULERDWR_ADDRESS 0x509c +/* Register: sdr.ctrlgrp.mppriority */ +#define SDR_CTRLGRP_MPPRIORITY_ADDRESS 0x50ac +/* Wide Register: sdr.ctrlgrp.mpweight */ +#define SDR_CTRLGRP_MPWEIGHT_ADDRESS 0x50b0 +/* Register: sdr.ctrlgrp.mpweight.mpweight_0 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS 0x50b0 +/* Register: sdr.ctrlgrp.mpweight.mpweight_1 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS 0x50b4 +/* Register: sdr.ctrlgrp.mpweight.mpweight_2 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS 0x50b8 +/* Register: sdr.ctrlgrp.mpweight.mpweight_3 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS 0x50bc +/* Register: sdr.ctrlgrp.mppacing.mppacing_0 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS 0x50c0 +/* Register: sdr.ctrlgrp.mppacing.mppacing_1 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS 0x50c4 +/* Register: sdr.ctrlgrp.mppacing.mppacing_2 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS 0x50c8 +/* Register: sdr.ctrlgrp.mppacing.mppacing_3 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS 0x50cc +/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_0 */ +#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS 0x50d0 +/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_1 */ +#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS 0x50d4 +/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_2 */ +#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS 0x50d8 +/* Wide Register: sdr.ctrlgrp.phyctrl */ +#define SDR_CTRLGRP_PHYCTRL_ADDRESS 0x5150 +/* Register: sdr.ctrlgrp.phyctrl.phyctrl_0 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS 0x5150 +/* Register: sdr.ctrlgrp.phyctrl.phyctrl_1 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_ADDRESS 0x5154 +/* Register: sdr.ctrlgrp.phyctrl.phyctrl_2 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_ADDRESS 0x5158 +/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_0 */ +/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_0 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150 +/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_1 */ +/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_1 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154 +/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_2 */ +/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_2 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158 + +/* Register template: sdr::ctrlgrp::ctrlcfg */ +#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_LSB 26 +#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_MASK 0x04000000 +#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_LSB 25 +#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_MASK 0x02000000 +#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_LSB 24 +#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_MASK 0x01000000 +#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 +#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 +#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 +#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 +#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 +#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 +#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 +#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 +#define SDR_CTRLGRP_CTRLCFG_GENDBE_LSB 14 +#define SDR_CTRLGRP_CTRLCFG_GENDBE_MASK 0x00004000 +#define SDR_CTRLGRP_CTRLCFG_GENSBE_LSB 13 +#define SDR_CTRLGRP_CTRLCFG_GENSBE_MASK 0x00002000 +#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_LSB 12 +#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_MASK 0x00001000 +#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 +#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 +#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 +#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 +#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 +#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 +#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 +#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 +#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 +#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 +/* Register template: sdr::ctrlgrp::dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 +#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 +#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 +#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 +#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 +#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 +#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 +#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 +#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 +#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 +#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 +#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 +#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 +#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 +#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 +#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 +#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 +#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 +#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff +/* Register template: sdr::ctrlgrp::dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 +#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 +#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 +#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 +#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 +#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 +#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 +#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 +#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 +#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 +#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 +#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 +#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 +#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 +#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 +#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff +/* Register template: sdr::ctrlgrp::dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 +#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 +#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 +#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 +#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 +#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 +#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 +#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f +/* Register template: sdr::ctrlgrp::dramifwidth */ +#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 +#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff +/* Register template: sdr::ctrlgrp::dramdevwidth */ +#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 +#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramintr */ +#define SDR_CTRLGRP_DRAMINTR_INTRCLR_LSB 4 +#define SDR_CTRLGRP_DRAMINTR_INTRCLR_MASK 0x00000010 +#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_LSB 3 +#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_MASK 0x00000008 +#define SDR_CTRLGRP_DRAMINTR_DBEMASK_LSB 2 +#define SDR_CTRLGRP_DRAMINTR_DBEMASK_MASK 0x00000004 +#define SDR_CTRLGRP_DRAMINTR_SBEMASK_LSB 1 +#define SDR_CTRLGRP_DRAMINTR_SBEMASK_MASK 0x00000002 +#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 +#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 +/* Register template: sdr::ctrlgrp::sbecount */ +#define SDR_CTRLGRP_SBECOUNT_COUNT_LSB 0 +#define SDR_CTRLGRP_SBECOUNT_COUNT_MASK 0x000000ff +/* Register template: sdr::ctrlgrp::dbecount */ +#define SDR_CTRLGRP_DBECOUNT_COUNT_LSB 0 +#define SDR_CTRLGRP_DBECOUNT_COUNT_MASK 0x000000ff +/* Register template: sdr.ctrlgrp.lowpwreq */ +#define SDR_CTRLGRP_LOWPWREQ_DEEPPWRDNREQ_LSB 0 +#define SDR_CTRLGRP_LOWPWREQ_DEEPPWRDNREQ_MASK 0x00000001 +#define SDR_CTRLGRP_LOWPWREQ_DEEPPWRDNMASK_LSB 1 +#define SDR_CTRLGRP_LOWPWREQ_DEEPPWRDNMASK_MASK 0x00000006 +#define SDR_CTRLGRP_LOWPWREQ_SELFRSHREQ_LSB 3 +#define SDR_CTRLGRP_LOWPWREQ_SELFRSHREQ_MASK 0x00000008 +#define SDR_CTRLGRP_LOWPWREQ_SELFRSHREQ_ENABLED 0x1 +#define SDR_CTRLGRP_LOWPWREQ_SELFRSHREQ_DISABLED 0x0 +#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 +#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 +#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_BOTH_CHIPS 0x3 +/* Register template: sdr::ctrlgrp::lowpwrack */ +#define SDR_CTRLGRP_LOWPWRACK_SELFRFSHACK_LSB 1 +#define SDR_CTRLGRP_LOWPWRACK_SELFRFSHACK_MASK 0x00000002 +/* Register template: sdr::ctrlgrp::staticcfg */ +#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 +#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 +#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 +#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 +#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 +#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 +/* Register template: sdr::ctrlgrp::ctrlwidth */ +#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 +#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 +/* Register template: sdr::ctrlgrp::cportwidth */ +#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 +#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff +/* Register template: sdr::ctrlgrp::cportwmap */ +#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 +#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff +/* Register template: sdr::ctrlgrp::cportrmap */ +#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 +#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff +/* Register template: sdr::ctrlgrp::rfifocmap */ +#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 +#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff +/* Register template: sdr::ctrlgrp::wfifocmap */ +#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 +#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff +/* Register template: sdr::ctrlgrp::cportrdwr */ +#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 +#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff +/* Register template: sdr::ctrlgrp::portcfg */ +#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 +#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 +#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 +#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::fifocfg */ +#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 +#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 +#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 +#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::mppriority */ +#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 +#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff +/* Wide Register template: sdr::ctrlgrp::mpweight */ +/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff +/* Wide Register template: sdr::ctrlgrp::mppacing */ +/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff +/* Wide Register template: sdr::ctrlgrp::mpthresholdrst */ +/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ +0xffffffff +/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ +0xffffffff +/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ +0x0000ffff +/* Register template: sdr::ctrlgrp::remappriority */ +#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 +#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff +/* Wide Register template: sdr::ctrlgrp::phyctrl */ +/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_MASK 0xfffff000 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ + (((x) << 12) & 0xfffff000) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_LSB 10 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_MASK 0x00000c00 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ + (((x) << 10) & 0x00000c00) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_LSB 9 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_MASK 0x00000200 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ + (((x) << 9) & 0x00000200) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_LSB 8 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_MASK 0x00000100 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ + (((x) << 8) & 0x00000100) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_LSB 6 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_MASK 0x000000c0 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ + (((x) << 6) & 0x000000c0) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_LSB 4 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_MASK 0x00000030 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ + (((x) << 4) & 0x00000030) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_LSB 2 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_MASK 0x0000000c +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ + (((x) << 2) & 0x0000000c) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_LSB 0 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_MASK 0x00000003 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ + (((x) << 0) & 0x00000003) +/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_LSB 12 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_MASK 0xfffff000 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ + (((x) << 12) & 0xfffff000) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_LSB 0 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_MASK 0x00000fff +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ + (((x) << 0) & 0x00000fff) +/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_LSB 0 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_MASK 0x00000fff +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ + (((x) << 0) & 0x00000fff) +/* Register template: sdr::ctrlgrp::dramodt */ +#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 +#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 +#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 +#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f +/* Field instance: sdr::ctrlgrp::dramsts */ +#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 +#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 + +/* To determine the duration of SDRAM test */ +/* quick test which run around 5s */ +#define SDRAM_TEST_FAST 0 +/* normal test which run around 30s */ +#define SDRAM_TEST_NORMAL 1 +/* long test which run in minutes */ +#define SDRAM_TEST_LONG 2 + +/* SDRAM width macro for configuration with ECC */ +#define SDRAM_WIDTH_32BIT_WITH_ECC 40 +#define SDRAM_WIDTH_16BIT_WITH_ECC 24 + +#endif +#endif /* _SDRAM_H_ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index c3d958c..5dce54a 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -10,6 +10,7 @@ #include "../../board/altera/socfpga/pinmux_config.h" #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" +#include "../../board/altera/socfpga/sdram/sdram_config.h"
/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH