On 17.08.16 09:13, Heiko Schocher wrote:
on at91sam9x5 PRES offset is 4 in the PMC master clock register.
Signed-off-by: Heiko Schocher hs@denx.de
arch/arm/mach-at91/arm926ejs/clock.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c8d24ae..e3181fa 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -162,7 +162,13 @@ int at91_clock_init(unsigned long main_clock) gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); freq = gd->arch.mck_rate_hz;
+#if defined(CONFIG_AT91SAM9X5)
- /* different in prescale on at91sam9x5 */
- freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
This one is really ugly ... I can live with the ifdef here but have you realized the 0x7 for PRES?
Andreas
+#else freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ +#endif
#if defined(CONFIG_AT91SAM9G20) /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?