The targets using dataflash and nandflash as storage, for both at91sam9261 and at91sam9g10 SoC are available.
Signed-off-by: Romain Izard romain.izard.pro@gmail.com --- MAKEALL | 2 - Makefile | 23 --- arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c | 32 ++-- arch/arm/include/asm/arch-at91/at91_matrix.h | 15 +- arch/arm/include/asm/arch-at91/at91sam9261.h | 1 + board/atmel/at91sam9261ek/at91sam9261ek.c | 211 +++++++++++--------- board/atmel/at91sam9261ek/config.mk | 1 - board/atmel/at91sam9261ek/led.c | 21 +-- boards.cfg | 6 + include/configs/at91sam9261ek.h | 101 ++++++---- 10 files changed, 220 insertions(+), 193 deletions(-) delete mode 100644 board/atmel/at91sam9261ek/config.mk
diff --git a/MAKEALL b/MAKEALL index 3aac7ca..6e97054 100755 --- a/MAKEALL +++ b/MAKEALL @@ -448,8 +448,6 @@ LIST_ARMV7=" \ LIST_at91="$(boards_by_soc at91)\ $(boards_by_soc at91rm9200)\ at91sam9260ek \ - at91sam9261ek \ - at91sam9g10ek \ at91sam9g20ek \ at91sam9m10g45ek \ at91sam9rlek \ diff --git a/Makefile b/Makefile index c62601a..b0edafb 100644 --- a/Makefile +++ b/Makefile @@ -766,29 +766,6 @@ M5485HFE_config : unconfig ## ARM926EJ-S Systems #########################################################################
-at91sam9261ek_nandflash_config \ -at91sam9261ek_dataflash_cs0_config \ -at91sam9261ek_dataflash_cs3_config \ -at91sam9261ek_config \ -at91sam9g10ek_nandflash_config \ -at91sam9g10ek_dataflash_cs0_config \ -at91sam9g10ek_dataflash_cs3_config \ -at91sam9g10ek_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 9g10,$@)" ] ; then \ - echo "#define CONFIG_AT91SAM9G10EK 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_AT91SAM9261EK 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91 - at91sam9rlek_nandflash_config \ at91sam9rlek_dataflash_config \ at91sam9rlek_dataflash_cs0_config \ diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c index b4353ef..0d087b8 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -23,45 +23,47 @@ */
#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9261.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h>
void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - writel(1 << AT91SAM9261_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); }
void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - writel(1 << AT91SAM9261_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); }
void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - writel(1 << AT91SAM9261_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); }
-void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); }
void at91_serial_hw_init(void) @@ -79,21 +81,21 @@ void at91_serial_hw_init(void) #endif
#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); + at91_seriald_hw_init(); #endif }
#ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */ - writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -123,14 +125,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */
/* Enable clock */ - writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h index a9ba9e9..4d566e3 100644 --- a/arch/arm/include/asm/arch-at91/at91_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91_matrix.h @@ -27,7 +27,7 @@
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) -#elif defined(CONFIG_AT91SAM9261) +#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) #elif defined(CONFIG_AT91SAM9263) #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) @@ -43,7 +43,7 @@ #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #define AT91_MATRIX_MASTERS 6 #define AT91_MATRIX_SLAVES 5 -#elif defined(CONFIG_AT91SAM9261) +#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #define AT91_MATRIX_MASTERS 1 #define AT91_MATRIX_SLAVES 5 #elif defined(CONFIG_AT91SAM9263) @@ -63,7 +63,7 @@ typedef struct at91_priority {
typedef struct at91_matrix { u32 mcfg[AT91_MATRIX_MASTERS]; -#if defined(CONFIG_AT91SAM9261) +#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) u32 scfg[AT91_MATRIX_SLAVES]; u32 res61_1[3]; u32 tcr; @@ -113,7 +113,7 @@ typedef struct at91_matrix {
#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
-#if defined CONFIG_AT91SAM9261 +#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ #define AT91_MATRIX_MCFG_RCB0 (1 << 0) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ @@ -143,7 +143,8 @@ typedef struct at91_matrix { /* Fixed Index of Default Master */ #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) -#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) +#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) || \ + defined(CONFIG_AT91SAM9260) #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) #endif
@@ -151,7 +152,7 @@ typedef struct at91_matrix { #if defined(CONFIG_AT91SAM9G45) #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9263) + defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9263) #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) #endif
@@ -235,7 +236,7 @@ typedef struct at91_matrix { #endif
/* USB Pad Pull-Up Control Register */ -#if defined(CONFIG_AT91SAM9261) +#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #define AT91_MATRIX_USBPUCR_PUON 0x40000000 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index c85fd29..4934590 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -126,6 +126,7 @@ */ #define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ #define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/* * SoC specific defines diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index de5cfae..510aa2c 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -23,15 +23,15 @@ */
#include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9261.h> -#include <asm/arch/at91sam9261_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) @@ -50,94 +50,100 @@ DECLARE_GLOBAL_DATA_PTR; static void at91sam9261ek_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
/* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa);
/* Configure SMC CS3 for NAND/SmartMedia */ #ifdef CONFIG_AT91SAM9G10EK - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); #else - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); #endif - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode);
/* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
- at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ - at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ } #endif
#ifdef CONFIG_DRIVER_DM9000 static void at91sam9261ek_dm9000_hw_init(void) { + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC; + /* Configure SMC CS2 for DM9000 */ #ifdef CONFIG_AT91SAM9G10EK - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + + writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[2].cycle); #else - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); #endif
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); + /* Configure Reset signal as output */ - at91_set_gpio_output(AT91_PIN_PC10, 0); + at91_set_pio_output(AT91_PIO_PORTC, 10, 0);
/* Configure Interrupt pin as input, no pull-up */ - at91_set_gpio_input(AT91_PIN_PC11, 0); + at91_set_pio_input(AT91_PIO_PORTC, 11, 0); } #endif
@@ -156,50 +162,52 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9261_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, };
void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 12, 0); /* power up */ }
void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 12, 1); /* power down */ }
static void at91sam9261ek_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ - at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ - at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ - at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ - at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ - at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ - at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */ + at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */ + at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */ + at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */ + at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ + at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ + + writel(AT91_PMC_HCK1, &pmc->scer);
#ifdef CONFIG_AT91SAM9G10EK gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE; #else - gd->fb_base = AT91SAM9261_SRAM_BASE; + gd->fb_base = ATMEL_BASE_SRAM; #endif }
@@ -217,7 +225,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; @@ -233,6 +241,18 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif
+int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + + return 0; +} + int board_init(void) { /* Enable Ctrlc */ @@ -246,9 +266,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); #endif @@ -273,8 +293,9 @@ int board_eth_init(bd_t *bis)
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; }
diff --git a/board/atmel/at91sam9261ek/config.mk b/board/atmel/at91sam9261ek/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/atmel/at91sam9261ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c index 5d1c5f2..99f0046 100644 --- a/board/atmel/at91sam9261ek/led.c +++ b/board/atmel/at91sam9261ek/led.c @@ -23,21 +23,18 @@ */
#include <common.h> -#include <asm/arch/at91sam9261.h> -#include <asm/arch/at91_pmc.h> +#include <asm/io.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h>
void coloured_LED_init(void) { - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); + /* Clock enabled in board_early_init_f() */ + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_YELLOW_LED, 1);
- at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); - - at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + at91_set_pio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_YELLOW_LED, 1); } diff --git a/boards.cfg b/boards.cfg index 5e2acdb..349fed6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -83,6 +83,12 @@ at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 +at91sam9261ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 +at91sam9261ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 +at91sam9261ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH +at91sam9g10ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 +at91sam9g10ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 +at91sam9g10ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH at91sam9263ek_dataflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:SYS_USE_DATAFLASH at91sam9263ek_nandflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 401478b..0626294 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -27,36 +27,52 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_AT91_LEGACY +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x21f00000
/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CONFIG_SYS_HZ 1000
-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#ifdef CONFIG_AT91SAM9G10EK -#define CONFIG_AT91SAM9G10 1 /* It's an Atmel AT91SAM9G10 SoC*/ +/* Define actual evaluation board type from used processor type */ +#ifdef CONFIG_AT91SAM9G10 +# define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK */ #else -#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +# define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK */ #endif -#define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1
+/* Misc CPU related */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
/* LCD */ #define CONFIG_LCD 1 @@ -65,20 +81,21 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 #define CONFIG_ATMEL_LCD 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + #ifdef CONFIG_AT91SAM9261EK #define CONFIG_ATMEL_LCD_BGR555 1 #else #define CONFIG_AT91SAM9G10_LCD_BASE 0x23E00000 /* LCD is no more in SRAM */ #endif -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */ +#define CONFIG_RED_LED AT91_PIO_PORTA, 23 /* the power led */ +#define CONFIG_GREEN_LED AT91_PIO_PORTA, 13 /* the user1 led */ +#define CONFIG_YELLOW_LED AT91_PIO_PORTA, 14 /* the user2 led */
#define CONFIG_BOOTDELAY 3
@@ -106,10 +123,21 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_CMD_USB 1
-/* SDRAM */ +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
/* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -126,14 +154,14 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD22 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 15
#endif
@@ -168,7 +196,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 @@ -216,9 +244,6 @@
#endif
-#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16