24 Apr
2014
24 Apr
'14
12:28 a.m.
On 03/18/2014 11:10 AM, Aneesh Bansal wrote:
Changes:
- L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S
- Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area.
- For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Ruchika Gupta ruchika.gupta@freescale.com Signed-off-by: Aneesh Bansal aneesh.bansal@freescale.com
Applied to u-boot-mpc85xx/master, thanks.
York