Dear Estevam,
I used GPIO 16 to generate the 25MHZ clock, using enable_fec_anatop_clock(1,ENET_25MHZ), in ; board_eth_init() function, but got 50 MHz on GPIO_16;
When I manually set the 0x20C_80E0 address(Analog ENET PLL Control Register) 0x8018_2000 on u-boot terminal, I saw 25 MHz on GPIO_16. With
struct iomuxc *const iomuxc_regs2 = (struct iomuxc *)0x020c80e0; setbits_le32(&iomuxc_regs2, 0x80182000);
but still see 50 MHz.
Are my register write (setbits_le32) function parameters correct? If correct, in which file and its function Should I set this ENET_PLL_control register?
Thanks and best regards.
Mehmet Ali
-----Original Message----- From: Fabio Estevam [mailto:festevam@gmail.com] Sent: Thursday, January 25, 2018 2:40 PM To: Mehmet Ali İPİN mehmet.ipin@pavotek.com.tr Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] FW: u-boot v2016 vs v2013
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On Thu, Jan 25, 2018 at 9:06 AM, Mehmet Ali İPİN mehmet.ipin@pavotek.com.tr wrote:
Dear Fabio,
I checked my PHY KSZ9021 schematic (we used i.mx6 Dual Light) with boundary devices sabre_light_revD(they used i.mx6 quad) KSZ9021. We both use same clock and data signals on both i.mx6 and PHY sides.
I saw 6.25 MHz clock signal on RGMII_TXCLK pin of i.mx6dl which is connected to the GTX_CLK input pin of PHY same as in sabre light. PHY is multiplying this clock with 5 and generating 31.25 MHz, which is connected back to the ENET_REF_CLK pin of i.mx6dl.
I guess either my global ethernet clock or its pll clock registers or their mask registers are not set correctly, to generate 25 MHz, instead of 6.25 MHz.
May be you know, how may I correct them?
Maybe you need to call enable_fec_anatop_clock() to adjust the FEC clock.