P1020RDB-PD has NAND with large page. All other P1/P2 RDB boards have NAND with small page. According to P1/P2 RM documentation, for NAND with large page it is needed to use 256 kB mapping and for small page just 32 kB.
Currenly in p1_p2_rdb_pc board code there is a mix of 32 kB and 1 MB settings which effetively restrict to just 32 kB. Fix this issue and set TLB, LAW and LBC OR registers which correct mapping size based on the selected board.
Note that E500 core does not support Book-E page of 32 kB, so choose 64 kB settings for TLB.
Signed-off-by: Pali Rohár pali@kernel.org --- board/freescale/p1_p2_rdb_pc/law.c | 4 ++++ board/freescale/p1_p2_rdb_pc/tlb.c | 11 +++++++++-- include/configs/p1_p2_rdb_pc.h | 4 ++-- 3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 80adf21a1183..60672d34e11c 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -19,8 +19,12 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS +#ifdef CONFIG_TARGET_P1020RDB_PD + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC), +#else SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif +#endif };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 5bbeae302ad0..a5b80762f0fc 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -78,10 +78,17 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE - /* *I*G - NAND */ +#ifdef CONFIG_TARGET_P1020RDB_PD + /* *I*G - NAND large page 256K */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), + 0, 7, BOOKE_PAGESZ_256K, 1), +#else + /* *I*G - NAND small page 64K (effective only 32K; e500 does not support BOOKE_PAGESZ_32K) */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64K, 1), +#endif #endif
#if defined(CONFIG_SYS_RAMBOOT) || \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index cf84f4045538..2ddf768f2c82 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -214,7 +214,7 @@ * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable * (early boot only) - * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 + * 0xff80_0000 0xff83_ffff NAND flash 32K/256K non-cacheable CS1/0 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffa1_ffff CPLD 128K non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 @@ -283,7 +283,7 @@ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ +#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ | OR_FCM_CST \