19 Sep
2009
19 Sep
'09
7:10 p.m.
On Sep 19, 2009, at 7:20 AM, Poonam Aggrwal wrote:
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/ P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com
based of git://git.am.freescale.net/mirrors/u-boot.git board/freescale/p1_p2_rdb/ddr.c | 29 ++++++++++++++++++++++++----- 1 files changed, 24 insertions(+), 5 deletions(-)
applied to 85xx.
- k