On 05/31/2016 08:17 AM, Prabhakar Kushwaha wrote:
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson calvin.johnson@nxp.com Signed-off-by: Makarand Pawagi makarand.pawagi@mindspeed.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com
Changes for v2: Sending as it is Changes for v3: Incorporated York's comments
- Placed SoC overview in README.soc
Changes for v4
- Incorporated Edward L Swarthout's comments
- Updated DDR speed
- Added defines for MMDC controller
<snip>
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h new file mode 100644 index 0000000..31411f7 --- /dev/null +++ b/include/fsl_mmdc.h @@ -0,0 +1,164 @@ +/*
- Copyright 2016 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef FSL_MMDC_H +#define FSL_MMDC_H
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000 +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954 +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
+#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680 +#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 +#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 +#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
+#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */ +#define WR_LVL_HW_EN 0x00000001
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ +#define MPR_COMPARE_EN 0x00000001
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ +#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ +#define AUTO_RD_CALIBRATION_EN 0x00000010
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000
+#define START_REFRESH 0x00000001
Are these values board-specific?
York