Signed-off-by: Robert P. J. Day rpjday@crashcourse.ca
---
one more bit of tidying in the area of u-boot i'm actually working in at the moment.
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 985a024..2a486e4 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -37,7 +37,7 @@ void ecc_print_status(void) printf("Memory Error Disable:\n"); printf(" Multiple-Bit Error Disable: %d\n", (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); - printf(" Sinle-Bit Error Disable: %d\n", + printf(" Single-Bit Error Disable: %d\n", (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); printf(" Memory Select Error Disable: %d\n\n", (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); @@ -273,7 +273,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) { - printf("Address not alligned on " + printf("Address not aligned on " "double word boundary\n"); return 1; } @@ -312,7 +312,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) { - printf("Address not alligned on " + printf("Address not aligned on " "double word boundary\n"); return 1; } diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 30606fb..c7ea94c 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -123,7 +123,7 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg) int i;
if (num_buses > MAX_BUSES) { - printf("%d PCI buses requsted, %d supported\n", + printf("%d PCI buses requested, %d supported\n", num_buses, MAX_BUSES);
num_buses = MAX_BUSES; diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 4fae19c..106704d 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -23,7 +23,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
- /* Caculate pin location and 2bit mask and dir */ + /* Calculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index f62e1b7..21ab015 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -599,7 +599,7 @@ long int spd_sdram()
/* * Empirically set ~MCAS-to-preamble override for DDR 2. - * Your milage will vary. + * Your mileage will vary. */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { @@ -843,7 +843,7 @@ long int spd_sdram()
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* - * Use timebase counter, get_timer() is not availabe + * Use timebase counter, get_timer() is not available * at this point of initialization yet. */ static __inline__ unsigned long get_tbms (void) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 1865626..2e91f51 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -170,7 +170,7 @@ int get_clocks(void) tsec1_clk = csb_clk / 3; break; default: - /* unkown SCCR_TSEC1CM value */ + /* unknown SCCR_TSEC1CM value */ return -2; } #endif @@ -191,7 +191,7 @@ int get_clocks(void) usbdr_clk = csb_clk / 3; break; default: - /* unkown SCCR_USBDRCM value */ + /* unknown SCCR_USBDRCM value */ return -3; } #endif @@ -212,7 +212,7 @@ int get_clocks(void) tsec2_clk = csb_clk / 3; break; default: - /* unkown SCCR_TSEC2CM value */ + /* unknown SCCR_TSEC2CM value */ return -4; } #elif defined(CONFIG_MPC8313) @@ -239,7 +239,7 @@ int get_clocks(void) usbmph_clk = csb_clk / 3; break; default: - /* unkown SCCR_USBMPHCM value */ + /* unknown SCCR_USBMPHCM value */ return -5; }
@@ -266,7 +266,7 @@ int get_clocks(void) enc_clk = csb_clk / 3; break; default: - /* unkown SCCR_ENCCM value */ + /* unknown SCCR_ENCCM value */ return -7; } #endif @@ -286,7 +286,7 @@ int get_clocks(void) sdhc_clk = csb_clk / 3; break; default: - /* unkown SCCR_SDHCCM value */ + /* unknown SCCR_SDHCCM value */ return -8; } #endif @@ -305,7 +305,7 @@ int get_clocks(void) tdm_clk = csb_clk / 3; break; default: - /* unkown SCCR_TDMCM value */ + /* unknown SCCR_TDMCM value */ return -8; } #endif @@ -345,7 +345,7 @@ int get_clocks(void) pciexp1_clk = csb_clk / 3; break; default: - /* unkown SCCR_PCIEXP1CM value */ + /* unknown SCCR_PCIEXP1CM value */ return -9; }
@@ -363,7 +363,7 @@ int get_clocks(void) pciexp2_clk = csb_clk / 3; break; default: - /* unkown SCCR_PCIEXP2CM value */ + /* unknown SCCR_PCIEXP2CM value */ return -10; } #endif @@ -383,7 +383,7 @@ int get_clocks(void) sata_clk = csb_clk / 3; break; default: - /* unkown SCCR_SATACM value */ + /* unknown SCCR_SATA1CM value */ return -11; } #endif @@ -413,7 +413,7 @@ int get_clocks(void)
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { - /* corecnf_tab_index is too high, possibly worng value */ + /* corecnf_tab_index is too high, possibly wrong value */ return -11; } switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { @@ -435,7 +435,7 @@ int get_clocks(void) core_clk = 3 * csb_clk; break; default: - /* unkown core to csb ratio */ + /* unknown core to csb ratio */ return -13; }
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 784f4ab..845861e 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -47,7 +47,7 @@ void cpu_init_f (volatile immap_t * im) (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); #endif
- /* Enable Time Base & Decrimenter (so we will have udelay()) */ + /* Enable Time Base & Decrementer (so we will have udelay()) */ im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
rday