Hi Nicolas,
On 22.04.2020 11:46, Nicolas Saenz Julienne wrote:
On Tue, 2020-04-21 at 18:50 +0200, Sylwester Nawrocki wrote:
From: Marek Szyprowski m.szyprowski@samsung.com
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge.
Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com
arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 4295356..6a748da 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -11,10 +11,15 @@ #include <dm/device.h> #include <fdt_support.h>
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
Where did you got this size from? I read from the Linux device tree the following:
pcie0: pcie@7d500000 { compatible = "brcm,bcm2711-pcie"; [...] ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; [...] };
Shouldn't the size be 0x4000000 then?
Other than that the patch looks good to me.
Well, I reduced the window to 0x800000 to make it fit somewhere nicely in the 32bit address space. We can limit it even to a single section (2MiB), that's more than needed by the XHCI controller anyway. I can add a comment about that.
Best regards