
21 Jun
2012
21 Jun
'12
7:01 p.m.
On Wed, May 30, 2012 at 10:46:00AM -0700, Steve Sakoman wrote:
The PLL setup values currently assume a 24 Mhz input clock.
This patch uses V_OSCK from the board config file to support boards with different input clock rates.
Signed-off-by: Steve Sakoman steve@sakoman.com
Queued up for u-boot-ti/master, thanks!
--
Tom