On Tue, Jun 18, 2019 at 2:22 PM Tudor.Ambarus@microchip.com wrote:
From: Cyrille Pitchen cyrille.pitchen@microchip.com
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.
Signed-off-by: Cyrille Pitchen cyrille.pitchen@microchip.com [tudor.ambarus@microchip.com: use "jedec,spi-nor", edit commit message] Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com
v5: no change v4: no change v3: no change v2: new patch
arch/arm/dts/at91-sama5d2_xplained.dts | 36 ++++++++++++++++------------------ 1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index c0708feeb7b2..7f0d1696ba3e 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -79,26 +79,18 @@ };
qspi0: spi@f0020000 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_qspi0_sck_cs_default &pinctrl_qspi0_dat_default>; status = "okay";u-boot,dm-pre-reloc;
I always believe, keeping period sync of DTS changes from linux rather than minimal or required changes when it needed. it is up to Eugen to make decision here.
Jagan.