To implement pinctrl support for the RK3368, we need to add the bit-definitions to configure the IOMUX and tie these into the pinctrl framework. This also adds the mapping from the IRQ# back onto the periheral id for the SPI devices.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 90 +++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c index 67695ab..7a3b7c16 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c @@ -1,8 +1,11 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan andy.yan@rock-chips.com + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * * SPDX-License-Identifier: GPL-2.0+ */ + #include <common.h> #include <dm.h> #include <errno.h> @@ -16,6 +19,25 @@
DECLARE_GLOBAL_DATA_PTR;
+/* PMUGRF_GPIO0B_IOMUX */ +enum { + GPIO0B5_MASK = GENMASK(11, 10), + GPIO0B5_GPIO = 0, + GPIO0B5_SPI2_CSN0 = (2 << 10), + + GPIO0B4_MASK = GENMASK(9, 8), + GPIO0B4_GPIO = 0, + GPIO0B4_SPI2_CLK = (2 << 8), + + GPIO0B3_MASK = GENMASK(7, 6), + GPIO0B3_GPIO = 0, + GPIO0B3_SPI2_TXD = (2 << 6), + + GPIO0B2_MASK = GENMASK(5, 4), + GPIO0B2_GPIO = 0, + GPIO0B2_SPI2_RXD = (2 << 4), +}; + /*GRF_GPIO0C_IOMUX*/ enum { GPIO0C7_MASK = GENMASK(15, 14), @@ -209,10 +231,12 @@ enum { GPIO1C7_MASK = GENMASK(15, 14), GPIO1C7_GPIO = 0, GPIO1C7_EMMC_DATA5 = (2 << 14), + GPIO1C7_SPI0_TXD = (3 << 14),
GPIO1C6_MASK = GENMASK(13, 12), GPIO1C6_GPIO = 0, GPIO1C6_EMMC_DATA4 = (2 << 12), + GPIO1C6_SPI0_RXD = (3 << 12),
GPIO1C5_MASK = GENMASK(11, 10), GPIO1C5_GPIO = 0, @@ -241,6 +265,10 @@ enum {
/* GRF_GPIO1D_IOMUX*/ enum { + GPIO1D5_MASK = GENMASK(11, 10), + GPIO1D5_GPIO = 0, + GPIO1D5_SPI0_CLK = (2 << 10), + GPIO1D3_MASK = GENMASK(7, 6), GPIO1D3_GPIO = 0, GPIO1D3_EMMC_PWREN = (2 << 6), @@ -252,10 +280,12 @@ enum { GPIO1D1_MASK = GENMASK(3, 2), GPIO1D1_GPIO = 0, GPIO1D1_EMMC_DATA7 = (2 << 2), + GPIO1D1_SPI0_CSN1 = (3 << 2),
GPIO1D0_MASK = GENMASK(1, 0), GPIO1D0_GPIO = 0, GPIO1D0_EMMC_DATA6 = (2 << 0), + GPIO1D0_SPI0_CSN0 = (3 << 0), };
@@ -331,6 +361,7 @@ enum { GPIO3D4_MASK = GENMASK(9, 8), GPIO3D4_GPIO = 0, GPIO3D4_MAC_TXCLK = (1 << 8), + GPIO3D4_SPI1_CNS1 = (2 << 8),
GPIO3D1_MASK = GENMASK(3, 2), GPIO3D1_GPIO = 0, @@ -377,6 +408,54 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, } }
+static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv, + int spi_id) +{ + struct rk3368_grf *grf = priv->grf; + struct rk3368_pmu_grf *pmugrf = priv->pmugrf; + + switch (spi_id) { + case PERIPH_ID_SPI0: + /* + * eMMC can only be connected with 4 bits, when SPI0 is used. + * This is all-or-nothing, so we assume that if someone asks us + * to configure SPI0, that their eMMC interface is unused or + * configured appropriately. + */ + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D0_MASK | GPIO1D1_MASK | + GPIO1D5_MASK, + GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 | + GPIO1D5_SPI0_CLK); + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C6_MASK | GPIO1C7_MASK, + GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD); + break; + case PERIPH_ID_SPI1: + /* + * We don't implement support for configuring SPI1_CSN#1, as it + * will conflicts with the GMAC (MAC TX clk-out). + */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B6_MASK | GPIO1B7_MASK, + GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0); + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C0_MASK | GPIO1C1_MASK, + GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD); + break; + case PERIPH_ID_SPI2: + rk_clrsetreg(&pmugrf->gpio0b_iomux, + GPIO0B2_MASK | GPIO0B3_MASK | + GPIO0B4_MASK | GPIO0B5_MASK, + GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD | + GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0); + break; + default: + debug("%s: spi id = %d iomux error!\n", __func__, spi_id); + break; + } +} + #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id) { @@ -457,6 +536,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_UART4: pinctrl_rk3368_uart_config(priv, func); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + pinctrl_rk3368_spi_config(priv, func); + break; case PERIPH_ID_EMMC: case PERIPH_ID_SDCARD: pinctrl_rk3368_sdmmc_config(priv->grf, func); @@ -495,6 +579,12 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_UART1; case 55: return PERIPH_ID_UART0; + case 44: + return PERIPH_ID_SPI0; + case 45: + return PERIPH_ID_SPI1; + case 41: + return PERIPH_ID_SPI2; case 35: return PERIPH_ID_EMMC; case 32: