On 29.08.2018 10:56, kostap@marvell.com wrote:
From: Ofer Heifetz oferh@marvell.com
When 2 commands are submitted in a row, and the second is very quick, the completion of the second command might never come. This happens especially if the second command is quick, such as a status read after an erase
This patch is taken from Linux: 'commit 21fc0ef9652f' ("mtd: nand: pxa3xx-nand: fix random command timeouts")
Signed-off-by: Chris Packham judge.packham@gmail.com Signed-off-by: Ofer Heifetz oferh@marvell.com Reviewed-by: Igal Liberman igall@marvell.com Cc: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org
drivers/mtd/nand/pxa3xx_nand.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 7b1dcb2..98bb4c6 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -623,8 +623,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) is_ready = 1; }
- /*
* Clear all status bit before issuing the next command, which* can and will alter the status bits and will deserve a new* interrupt on its own. This lets the controller exit the IRQ*/- nand_writel(info, NDSR, status);
- if (status & NDSR_WRCMDREQ) {
nand_writel(info, NDSR, NDSR_WRCMDREQ);@@ -645,8 +651,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) nand_writel(info, NDCB0, info->ndcb3); }
- /* clear NDSR to let the controller exit the IRQ */
- nand_writel(info, NDSR, status); if (is_completed) info->cmd_complete = 1; if (is_ready)
Applied to u-boot-marvell/master
Thanks, Stefan