This patch is used to generate a special version u-boot, together with the data structure on the SDcard/SPI flash, can be used to booting from SDcard/SPI flash on 8536DS board.
The boot ROM in CPU and the data structure on SD card will initialize the DDR, set a large tlb0 for DDR and CCSR, set law0 for DDR. The special version uboot avoid initializing the DDR. Try to reseve the law0 for DDR by adding a CONFIG_SYS_RESERVED_LAW0 macro for the "dynamic law allocation" code. But keep the original tlb initialize code for DDR, disabled the large tlb0 which was set in the boot ROM.
This patch is intend for those who are interested in the function of booting from SD card on 8536DS board and not for opensource. An utility is needed to write the data structure and the special version u-boot onto the SD card which has filesystem on it or onto the SPI flash.
Signed-off-by: Jason Jin Jason.jin@freescale.com Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com --- Makefile | 12 +++ board/freescale/mpc8536ds/config.mk | 2 + board/freescale/mpc8536ds/mpc8536ds.c | 4 + board/freescale/mpc8536ds/tlb.c | 3 + board/freescale/mpc8536ds/u-boot-sdboot.lds | 139 +++++++++++++++++++++++++++ config.mk | 4 +- cpu/mpc85xx/cpu_init.c | 70 +++++++++++++- cpu/mpc85xx/start.S | 17 +++- drivers/misc/fsl_law.c | 4 + include/configs/MPC8536DS.h | 12 ++- 10 files changed, 262 insertions(+), 5 deletions(-) create mode 100644 board/freescale/mpc8536ds/u-boot-sdboot.lds
diff --git a/Makefile b/Makefile index e8b4c13..c18a2e0 100644 --- a/Makefile +++ b/Makefile @@ -2360,6 +2360,18 @@ ATUM8548_config: unconfig MPC8536DS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8536ds freescale
+MPC8536DS_SPIFLASH_config \ +MPC8536DS_SDCARD_config: unconfig + @echo "" >$(obj)include/config.h; + @if [ "$(findstring _SPIFLASH_,$@)" ] ; then \ + echo "#define CONFIG_SPIFLASH_U_BOOT" >> $(obj)include/config.h ; \ + fi ; + @echo "#define CONFIG_SDCARD_U_BOOT" >> $(obj)include/config.h ; + @$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale ; \ + echo "TEXT_BASE = 0x11001000" > $(obj)board/freescale/mpc8536ds/config.tmp ; \ + echo "#define CONFIG_SDCARD_U_BOOT" >> $(obj)include/config.h ; \ + echo "CONFIG_SDCARD_U_BOOT = y" >> $(obj)include/config.mk ; + MPC8540ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index 9775ff4..b1c6251 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -23,6 +23,8 @@ # # mpc8536ds board # +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 1f028c2..f4ce72f 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -73,6 +73,10 @@ initdram(int board_type)
puts("Initializing....");
+#ifdef CONFIG_SDCARD_U_BOOT + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif + #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); #else diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index 35a13d4..cb570ef 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -27,6 +27,8 @@ #include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = { + +#if !defined(CONFIG_SDCARD_U_BOOT) /* TLB 0 - for temp stack in cache */ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -40,6 +42,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), +#endif
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/mpc8536ds/u-boot-sdboot.lds b/board/freescale/mpc8536ds/u-boot-sdboot.lds new file mode 100644 index 0000000..f4a0e91 --- /dev/null +++ b/board/freescale/mpc8536ds/u-boot-sdboot.lds @@ -0,0 +1,139 @@ +/* + * Copyright (C)2009 Freescale Semiconductor, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + .resetvec ADDR(.text) + 0x7fffc - 0x1000 : + { + *(.resetvec) + } = 0xffff + + . = ADDR(.text) + 0x80000 - 0x1000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/config.mk b/config.mk index b1254e9..3300b75 100644 --- a/config.mk +++ b/config.mk @@ -112,8 +112,8 @@ DBGFLAGS= -g # -DDEBUG OPTFLAGS= -Os #-fomit-frame-pointer ifndef LDSCRIPT #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug -ifeq ($(CONFIG_NAND_U_BOOT),y) -LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +ifeq ($(CONFIG_SDCARD_U_BOOT),y) +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-sdboot.lds else LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0b7c609..f2fd168 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,9 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright (C) 2007,2009 Freescale Semiconductor, Inc. + * + * (C) 2009 Freescale Semiconductor, Inc. + * Modified by Jason Jin, Jason.jin@freescale.com, + * Mingkai hu, Mingkai.hu@freescale.com * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -164,6 +168,70 @@ void cpu_init_early_f(void) init_tlbs(); }
+#ifdef CONFIG_SDCARD_U_BOOT +/* + * Used for booting from SD. + * The ROM code has set a 4G space in tlb0, and on the sd data structure, + * there also has a law0 setting for DDR(usually 1G, can be changed). + * we try to use those space as much as we can and will change those + * setting later. + * Change the CCSRBAR firstly as needed. +*/ +void cpu_init_early_f_sd(void) +{ + unsigned int law_size; + + /* set up CCSR if we want it moved */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) + { + u32 temp; + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT); + out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12); + + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); + } +#endif + + /* Pointer is writable since we allocated a register for it. + * the gd->used_law will be used in the init_laws(), + * we prepared it here. + */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* law0 has been set for DDR in the SD data structure, we defined a + * CFG_RESERVED_LAW macro in the header file, try to avoid it being + * overlaped in the init_laws(). + */ + init_laws(); + + /*set a temp tlb15 in address space 1 for DDR*/ + set_tlb(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 1, 15, BOOKE_PAGESZ_1G, 1); + + /*And tlb14 for CCSR registers*/ + set_tlb(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 14, BOOKE_PAGESZ_1M, 1); +} + +/*This run in space 1 */ +void cpu_init_early_f_sd_continue(void) +{ + /* Disable tlb0 which intialized in the ROM + * Normal init for space 0 + */ + disable_tlb(0); + init_tlbs(); + + /*Reinitialize the tlb for DDR in space 0*/ + setup_ddr_tlbs(CONFIG_SYS_SDRAM_SIZE); +} +#endif + /* * Breathe some life into the CPU... * diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 80f9677..4601c0a 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -184,6 +184,7 @@ _start_e500: mtspr DBCR0,r0 #endif
+#if !defined(CONFIG_SDCARD_U_BOOT) /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l @@ -254,9 +255,10 @@ switch_as: dcbtls 0,r0,r3 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b +#endif
/* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SDCARD_U_BOOT) b _start_cont #else /* Calculate absolute address in FLASH and jump there */ @@ -296,7 +298,20 @@ _start_cont: stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT +#if !defined(CONFIG_SDCARD_U_BOOT) bl cpu_init_early_f +#else + bl cpu_init_early_f_sd + + /*Then switch to space 1*/ + lis r3,(MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS)@h + ori r3,r3,(MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS)@l + mtmsr r3 + isync + msync + + bl cpu_init_early_f_sd_continue +#endif
/* switch back to AS = 0 */ lis r3,(MSR_CE|MSR_ME|MSR_DE)@h diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 58340c1..1d709dd 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -168,6 +168,10 @@ void init_laws(void)
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
+#ifdef CONFIG_SDCARD_U_BOOT + gd->used_laws |= (1 << CONFIG_SYS_RESERVED_LAW0); +#endif + for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index bbb448d..b19f028 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_SPD_BUS_NUM 1
/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ +#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 @@ -235,9 +235,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
+#if !defined(CONFIG_SDCARD_U_BOOT) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ +#else +#undef CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* we have SDRAM initialized */ +#endif
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) @@ -246,6 +252,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+#ifdef CONFIG_SDCARD_U_BOOT +#define CONFIG_SYS_RESERVED_LAW0 0 +#endif + #define CONFIG_SYS_NAND_BASE 0xffa00000 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\