Use dram config variable name as sys_reg2 instead of sys_reg since the final variable value is to written into a pmugrf register named as sys_reg2.
This reflect the both variable and associated register names are same and also help to add next sys_reg's to add it in future.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: YouMin Chen cym@rock-chips.com --- drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 3241bc285e..4463fc84c8 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1005,11 +1005,11 @@ static void set_ddrconfig(const struct chan_info *chan, static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *sdram_params) { - u32 sys_reg = 0; + u32 sys_reg2 = 0; unsigned int channel, idx;
- sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype); - sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels); + sys_reg2 |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype); + sys_reg2 |= SYS_REG_ENC_NUM_CH(sdram_params->base.num_channels); for (channel = 0, idx = 0; (idx < sdram_params->base.num_channels) && (channel < 2); channel++) { @@ -1021,15 +1021,15 @@ static void dram_all_config(struct dram_info *dram, if (sdram_params->ch[channel].col == 0) continue; idx++; - sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel); - sys_reg |= SYS_REG_ENC_CHINFO(channel); - sys_reg |= SYS_REG_ENC_RANK(info->rank, channel); - sys_reg |= SYS_REG_ENC_COL(info->col, channel); - sys_reg |= SYS_REG_ENC_BK(info->bk, channel); - sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel); - sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); - sys_reg |= SYS_REG_ENC_BW(info->bw, channel); - sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel); + sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel); + sys_reg2 |= SYS_REG_ENC_CHINFO(channel); + sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel); + sys_reg2 |= SYS_REG_ENC_COL(info->col, channel); + sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel); + sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel); + sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); + sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel); + sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel);
ddr_msch_regs = dram->chan[channel].msch; noc_timing = &sdram_params->ch[channel].noc_timings; @@ -1050,7 +1050,7 @@ static void dram_all_config(struct dram_info *dram, 1 << 17); }
- writel(sys_reg, &dram->pmugrf->os_reg2); + writel(sys_reg2, &dram->pmugrf->os_reg2); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, sdram_params->base.stride << 10);