Add NAND support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinberg@compulab.co.il Cc: Stefano Babic sbabic@denx.de Cc: Tom Rini trini@ti.com Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_fx6/cm_fx6.c | 38 ++++++++++++++++++++++++++++++++++++++ board/compulab/cm_fx6/spl.c | 9 +++++++++ include/configs/cm_fx6.h | 14 ++++++++++++++ 3 files changed, 61 insertions(+)
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b55b99e..6d37c21 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -9,10 +9,46 @@ */
#include <common.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> #include "common.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void cm_fx6_setup_gpmi_nand(void) +{ + SETUP_IOMUX_PADS(nand_pads); + /* Enable clock roots */ + enable_usdhc_clk(1, 3); + enable_usdhc_clk(1, 4); + + setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); +} +#else +static void cm_fx6_setup_gpmi_nand(void) {} +#endif + #ifdef CONFIG_FSL_ESDHC int board_mmc_init(bd_t *bis) { @@ -33,6 +69,8 @@ int board_mmc_init(bd_t *bis) int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + cm_fx6_setup_gpmi_nand(); + return 0; }
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index 9f9e5f8..5c432b4 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -15,6 +15,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> #include <asm/imx-common/iomux-v3.h> #include <fsl_esdhc.h> #include "common.h" @@ -355,7 +356,15 @@ static void cm_fx6_setup_ecspi(void) { }
void board_init_f(ulong dummy) { + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + gd = &gdata; + /* + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot + * initializes DMA very early (before all board code), so the only + * opportunity we have to initialize APBHDMA clocks is in SPL. + */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); enable_usdhc_clk(1, 2); arch_cpu_init(); timer_init(); diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 285af33..973150f 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -179,6 +179,20 @@ #define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_WINBOND
+/* NAND */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_MXS +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* APBH DMA is required for NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + /* GPIO */ #define CONFIG_MXC_GPIO