Report about my problem.
Bodhi said to send my report to this address
main topic thread here
https://forum.openwrt.org/t/u-boot-tm7621a-mempll-3pll-mode-calibration-fail...
Thanks a lot guys!!!
Alan
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31000000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL3 FB_DL: 0x14, 1/0 = 609/415 51000000
MEMPLL 3PLL mode calibration fail
do DDR setting..[01F40000]
Apply DDR2 Setting...(use default AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0007:| 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0008:| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0009:| 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0011:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 56
B:| 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0
opt_dle value:5
DRAMC_DDR2CTL[07c]=40001253
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=00000000
DRAMC_DQIDLY2[214]=00000000
DRAMC_DQIDLY3[218]=00000000
DRAMC_DQIDLY4[21c]=00000000
DRAMC_R0DELDLY[018]=00000000
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 0 0 0 0 0 0 0 0 0 0
10 | 0 0 0 0 0 0
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =0 DQS1 = 0
==================================================================
bit DQS0 bit DQS1
0 (-1~-1)0 8 (-1~-1)0
1 (-1~-1)0 9 (-1~-1)0
2 (-1~-1)0 10 (-1~-1)0
3 (-1~-1)0 11 (-1~-1)0
4 (-1~-1)0 12 (-1~-1)0
5 (-1~-1)0 13 (-1~-1)0
6 (-1~-1)0 14 (-1~-1)0
7 (-1~-1)0 15 (-1~-1)0
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 0 0 0 0 0 0 0 0 0 0
10 | 0 0 0 0 0 0
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffffffff
DQS loop = 14, cmp_err_1 = ffffffff
DQS loop = 13, cmp_err_1 = ffffffff
DQS loop = 12, cmp_err_1 = ffffffff
DQS loop = 11, cmp_err_1 = ffffffff
DQS loop = 10, cmp_err_1 = ffffffff
DQS loop = 9, cmp_err_1 = ffffffff
DQS loop = 8, cmp_err_1 = ffffffff
DQS loop = 7, cmp_err_1 = ffffffff
DQS loop = 6, cmp_err_1 = ffffffff
DQS loop = 5, cmp_err_1 = ffffffff
DQS loop = 4, cmp_err_1 = ffffffff
DQS loop = 3, cmp_err_1 = ffffffff
DQS loop = 2, cmp_err_1 = ffffffff
DQS loop = 1, cmp_err_1 = ffffffff
DQS loop = 0, cmp_err_1 = ffffffff
DQ loop=15, cmp_err_1 = ffffffff
DQ loop=14, cmp_err_1 = ffffffff
DQ loop=13, cmp_err_1 = ffffffff
DQ loop=12, cmp_err_1 = ffffffff
DQ loop=11, cmp_err_1 = ffffffff
DQ loop=10, cmp_err_1 = ffffffff
DQ loop=9, cmp_err_1 = ffffffff
DQ loop=8, cmp_err_1 = ffffffff
DQ loop=7, cmp_err_1 = ffffffff
DQ loop=6, cmp_err_1 = ffffffff
DQ loop=5, cmp_err_1 = ffffffff
DQ loop=4, cmp_err_1 = ffffffff
DQ loop=3, cmp_err_1 = ffffffff
DQ loop=2, cmp_err_1 = ffffffff
DQ loop=1, cmp_err_1 = ffffffff
DQ loop=0, cmp_err_1 = ffffffff
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=125000000 HZ
===================================================================
-- Alan