On Tue, Dec 15, 2009 at 02:37:59PM +0000, Nick Thompson wrote:
+/*
- Exploit the little endianness of the ARM to do multi-byte transfers
- per device read. This can perform over twice as quickly as individual
- byte transfers when buffer alignment is conducive.
- NOTE: This only works if the NAND is not connected to the 2 LSBs of
- the address bus. On Davinci EVM platforms this has always been true.
- */
+static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{
- struct nand_chip *chip = mtd->priv;
- const u32 *nand = chip->IO_ADDR_R;
- if ((((int)buf | len) & 0x3) == 0)
while (len > 0) {*(u32 *)buf = readl(nand);buf += 4;len -= 4;}
It's unlikely to actually happen with the current NAND code, but this could accelarate some additional cases as:
if ((((uintptr_t)buf) & 3) == 0) { while (len >= 4) { ... } }
- else if ((((int)buf | len) & 0x1) == 0)
while (len > 0) {*(u16 *)buf = readw(nand);buf += 2;len -= 2;}- else
while (len-- > 0)*buf++ = readb(nand);
We generally put brances around multi-line "if" bodies (especially complex ones), even if it's technically one statement.
- unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
- unsigned int const1 = 0, const2 = 0;
- unsigned char count1 = 0;
- unsigned int hw_4ecc[4];
- unsigned int const1;
- unsigned char count1;
Maybe further change "count1" to "i" and "const1" to "i * 2" (the code generated should be the same)? Similarly, it would be nice if we could do something with "pspare"/"pspare1" further on (even pspare[2] or pspare1/pspare2 would be nicer).
Or maybe that could be converted to autoinc as well, with some statement splitting to introduce the necessary sequence points.
Other than cosmetic issues, this looks OK. I'll be on vacation until the end of the year, so ACK a cleaned-up patch if someone wants to apply it before I get back.
-Scott