Differently from other Lcd signals, HSYNC and VSYNC signals result inverted if their bits are cleared to 0.
Invert their settings of IO_POL register.
Signed-off-by: Giulio Benetti giulio.benetti@micronovasrl.com --- drivers/video/sunxi/lcdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 4cb86fb..007057c 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -132,9 +132,9 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, }
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase); - if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW) + if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= SUNXI_LCDC_TCON_HSYNC_MASK; - if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW) + if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= SUNXI_LCDC_TCON_VSYNC_MASK;
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH