move gmii_sel register defines from board code to common place.
Signed-off-by: Heiko Schocher hs@denx.de Cc: Chandan Nath chandan.nath@ti.com Cc: Sandeep Paulraj s-paulraj@ti.com Cc: Tom Rini trini@ti.com Cc: Lars Poeschel poeschel@lemonage.de Cc: Enric Balletbo i Serra eballetbo@iseebcn.com
--- - changes for v2: defined all bits used in the gmii_sel register as Tom Rini suggested
arch/arm/include/asm/arch-am33xx/cpu.h | 21 +++++++++++++++++++++ board/isee/igep0033/board.c | 7 ++----- board/phytec/pcm051/board.c | 2 -- board/ti/am335x/board.c | 6 +----- 4 Dateien geändert, 24 Zeilen hinzugefügt(+), 12 Zeilen entfernt(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index fb44654..98e15c0 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -364,6 +364,27 @@ struct ctrl_dev { unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ }; + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII1_SEL_NOTUSED 0x3 +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define GMII2_SEL_NOTUSED 0xc +#define RGMII1_IDMODE BIT(4) +#define RGMII2_IDMODE BIT(5) +#define RMII1_IO_CLK_EN BIT(6) +#define RMII2_IO_CLK_EN BIT(7) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 842051f..d7cf7d0 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -36,10 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -/* MII mode defines */ -#define RMII_MODE_ENABLE 0x4D - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static const struct ddr_data ddr3_data = { @@ -182,7 +178,8 @@ int board_eth_init(bd_t *bis) eth_setenv_enetaddr("ethaddr", mac_addr); }
- writel(RMII_MODE_ENABLE, &cdev->miisel); + writel((GMII1_SEL_RMII | GMII2_SEL_NOTUSED | RMII1_IO_CLK_EN), + &cdev->miisel);
rv = cpsw_register(&cpsw_data); if (rv < 0) diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 72c5612..d0314e4 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -41,8 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
/* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA #define RMII_RGMII2_MODE_ENABLE 0x49
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index b04e385..6b96f84 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -39,10 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-/* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0x3A - /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7
@@ -465,7 +461,7 @@ int board_eth_init(bd_t *bis) cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { - writel(RGMII_MODE_ENABLE, &cdev->miisel); + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; }