From: Priyanka Jain Priyanka.Jain@freescale.com
LS2088A is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)Process to release secondary cores is different 4)LS2088A SoC has TZASC controller
In preparation of using same binary for LS2088A and LS2080A as both are using same development boards. code is update to detect difference based on SVR at runtime
Priyanka Jain (5): armv8: lsch3: Use SVR based timer base address detection armv8: fsl-layerscape: Update TZASC registers type armv8: fsl-layerscape : Check SVR for initializing TZASC armv8: fsl-layerscape: Add NXP LS2088A SoC support armv8/fsl-lsch3: Update code to release secondary cores
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 16 +++++- arch/arm/cpu/armv8/fsl-layerscape/cpu.h | 1 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 47 +++++++++++----- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 59 ++++++++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 7 ++- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 10 +++ board/freescale/ls2080a/MAINTAINERS | 2 +- board/freescale/ls2080aqds/MAINTAINERS | 2 +- board/freescale/ls2080aqds/README | 12 ++-- board/freescale/ls2080ardb/MAINTAINERS | 2 +- board/freescale/ls2080ardb/README | 8 +- 15 files changed, 198 insertions(+), 37 deletions(-)