Hello Sekhar,
Thank you for the advice below and sorry for the late reply; I have been offline for a week and I am catching up with my correspondence only now.
El 26/04/2010, a las 13:56, Nori, Sekhar escribió: [...]
The only delays being configured in the driver are the chip-select hold time delays which should not matter here as you see delays inserted between bytes which are part of a single transfer. I am starting to doubt peripheral mis-configuration as a possible cause here.
As you say chip-select hold time delays should not matter in this case. WDELAY and WDEL (respectively in SPIFMT and SPIDAT1 registers) control delay between transmissions, but they are both set to zero (disabled). So I believe slow RAM (and SPI module register) access is the most likely cause.
One way to mitigate the slow access to RAM would be to take advantage of external RAM burst by using EDMA. That will be some work because there is no other example of EDMA usage in U-Boot.
Thanks -- Delio