On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
The A10 clock manager parsed DT bindings generated by Quartus the bsp-editor to configure the A10 clocks. Sadly, those DT bindings changed at some point. The clock manager patch used the old ones, this patch replaces the bindings parser with one for the new set.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org
arch/arm/mach-socfpga/clock_manager_arria10.c | 158 ++++++++++++++------- .../include/mach/clock_manager_arria10.h | 2 +- 2 files changed, 111 insertions(+), 49 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 4ee6a82b5f..defa2f6261 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -9,6 +9,9 @@ #include <dm.h> #include <asm/arch/clock_manager.h> +static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
static u32 eosc1_hz; static u32 cb_intosc_hz; static u32 f2s_free_hz; @@ -64,89 +67,150 @@ struct perpll_cfg { u32 cntr8clk_cnt; u32 cntr8clk_src; u32 cntr9clk_cnt;
- u32 cntr9clk_src;
Why add this? I believe this is not exist.
It exists in the altera sources and it matches the pattern. What do you mean by "this is not exist" ?
u32 emacctl_emac0sel; u32 emacctl_emac1sel; u32 emacctl_emac2sel; u32 gpiodiv_gpiodbclk; };
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