With the default value of MDIO_CLK_DIV generatee MDC is too high and It is violating the IEEE specs much higher than 2.5Mhz.
Although there is errata(A-006260) for EMI2(MDIO2), but same errata is been hit on EMI1(MDIO1). unfortunately this errata never hit on B4 rev1. So reduced the MDIO_CLK_DIV value.
Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- board/freescale/b4860qds/b4_pbi.cfg | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg index 57b726e..05377ba 100644 --- a/board/freescale/b4860qds/b4_pbi.cfg +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -22,6 +22,9 @@ 09110024 00100008 09110028 00100008 0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 #Flush PBL data 09138000 00000000 091380c0 00000000