This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM.
Signed-off-by: Stefan Roese sr@denx.de ---
arch/mips/mach-octeon/dram.c | 41 ++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 0ad3d87e91..44abc6728e 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -12,17 +12,44 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - /* - * No DDR init yet -> run in L2 cache - */ - gd->ram_size = (4 << 20); - gd->bd->bi_dram[0].size = gd->ram_size; - gd->bd->bi_dram[1].size = 0; + if (IS_ENABLED(CONFIG_RAM_OCTEON)) { + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + + gd->ram_size = ram.size; + debug("SDRAM base=%lx, size=%lx\n", + (unsigned long)ram.base, (unsigned long)ram.size); + } else { + /* + * No DDR init yet -> run in L2 cache + */ + gd->ram_size = (4 << 20); + gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[1].size = 0; + }
return 0; }
ulong board_get_usable_ram_top(ulong total_size) { - return gd->ram_top; + if (IS_ENABLED(CONFIG_RAM_OCTEON)) { + /* Map a maximum of 256MiB - return not size but address */ + return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, 0x10000000ull); + } else { + return gd->ram_top; + } }