On Wed, 30 Jan 2019 07:07:10 +0000 Peng Fan peng.fan@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski [mailto:lukma@denx.de] Sent: 2019年1月30日 14:54 To: Peng Fan peng.fan@nxp.com Cc: sbabic@denx.de; Fabio Estevam fabio.estevam@nxp.com; dl-uboot-imx uboot-imx@nxp.com; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
Hi Peng,
-----Original Message----- From: Lukasz Majewski [mailto:lukma@denx.de] Sent: 2019年1月30日 7:19 To: Peng Fan peng.fan@nxp.com Cc: sbabic@denx.de; Fabio Estevam fabio.estevam@nxp.com; dl-uboot-imx uboot-imx@nxp.com; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 20/20] imx: add i.MX8MM EVK board support
Hi Peng,
Add i.MX8MM EVK board support.
Add board and SoC dts Add ddr training code support SD/MMC/GPIO/PINCTRL/UART
U-Boot SPL 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800) Normal Boot Trying to boot from MMC1
U-Boot 2019.01-00148-g1179cffe66 (Jan 28 2019 - 17:37:34 +0800)
CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz Reset cause: POR Model: NXP i.MX8MM EVK board DRAM: 2 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 In: serial Out: serial Err: serial DM
You set/adjust latter in the code the fec network driver. Why it is not found?
I dropped network support, could add it in V2.
From the patch it seems like the ETH is fully supported, at lease from the source code point of view.
Could you also share the output of "dm tree" command?
Sure.
I suppose/guess that this board shall support as much as possible of the DT/DM conversions?
Ok.
And I would like to emphasize the need of DDR training code (as a functions, not pair of offset and value).
Are you able to provide such code in the next version of the patch?
There is already common code under drivers/ddr/imx8m
Yes. Indeed there code is there.
For the array in board file, It need ddr tool change, out of my knowledge.
If the code is there - why not use it for this board? In that way we would kill two birds with one stone - the code would be tested on "blessed" NXP's development board.
Thanks, Peng.
Regards, Peng.
Hit any key to stop autoboot: 2
Signed-off-by: Peng Fan peng.fan@nxp.com
arch/arm/dts/fsl-imx8mm-evk.dts | 203 +++ arch/arm/dts/fsl-imx8mm.dtsi | 586 ++++++++ arch/arm/mach-imx/imx8m/Kconfig | 7 + board/freescale/imx8mm_evk/Kconfig | 12 + board/freescale/imx8mm_evk/MAINTAINERS | 6 + board/freescale/imx8mm_evk/Makefile | 12 + board/freescale/imx8mm_evk/imx8mm_evk.c | 144 ++ board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++++++++++ board/freescale/imx8mm_evk/spl.c | 187 +++ configs/imx8mm_evk_defconfig | 41 + include/configs/imx8mm_evk.h | 221 ++++ 11 files changed, 3399 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644 arch/arm/dts/fsl-imx8mm.dtsi create mode 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS create mode 100644 board/freescale/imx8mm_evk/Makefile create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mm_evk/spl.c create mode 100644 configs/imx8mm_evk_defconfig create mode 100644 include/configs/imx8mm_evk.h
diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644 index 0000000000..df409eca47 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm-evk.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 NXP
- */
+/dts-v1/;
+#include "fsl-imx8mm.dtsi"
+/ {
- model = "NXP i.MX8MM EVK board";
- compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
- chosen {
stdout-path = &uart2;- };
- regulators {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;reg_usdhc2_vmmc: regulator-usdhc2 {compatible = "regulator-fixed";regulator-name = "VSD_3V3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;off-on-delay = <20000>;enable-active-high;};- };
+};
+&iomuxc {
- pinctrl-names = "default";
- imx8mm-evk {
pinctrl_fec1: fec1grp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;};pinctrl_gpio_led: gpioledgrp {fsl,pins = <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;};pinctrl_uart2: uart2grp {fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;};pinctrl_usdhc2_gpio: usdhc2grpgpio {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;};pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;};pinctrl_usdhc2_100mhz: usdhc2grp100mhz {fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;};pinctrl_usdhc2_200mhz: usdhc2grp200mhz {fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;};pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;};pinctrl_usdhc3_100mhz: usdhc3grp100mhz {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;};pinctrl_usdhc3_200mhz: usdhc3grp200mhz {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;};pinctrl_wdog: wdoggrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;};- };
+};
+&uart2 { /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
+};
+&usdhc2 {
- pinctrl-names = "default", "state_100mhz",
"state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>,
<&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
<&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
<&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
+};
+&usdhc3 {
- pinctrl-names = "default", "state_100mhz",
"state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
+};
+&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
+}; diff --git a/arch/arm/dts/fsl-imx8mm.dtsi b/arch/arm/dts/fsl-imx8mm.dtsi new file mode 100644 index 0000000000..8a808f856d --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm.dtsi @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright 2017-2019 NXP
- */
+#include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pins-imx8mm.h> +#include <dt-bindings/thermal/thermal.h>
+/ {
- compatible = "fsl,imx8mm";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- aliases {
i2c0 = &i2c1;i2c1 = &i2c2;i2c2 = &i2c3;i2c3 = &i2c4;serial0 = &uart1;serial1 = &uart2;serial2 = &uart3;serial3 = &uart4;spi0 = &ecspi1;spi1 = &ecspi2;spi2 = &ecspi3;mmc0 = &usdhc1;mmc1 = &usdhc2;mmc2 = &usdhc3;gpio0 = &gpio1;gpio1 = &gpio2;gpio2 = &gpio3;gpio3 = &gpio4;gpio4 = &gpio5;- };
- cpus {
#address-cells = <1>;#size-cells = <0>;A53_0: cpu@0 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x0>;enable-method = "psci";next-level-cache = <&A53_L2>;};A53_1: cpu@1 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x1>;enable-method = "psci";next-level-cache = <&A53_L2>;};A53_2: cpu@2 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x2>;enable-method = "psci";next-level-cache = <&A53_L2>;};A53_3: cpu@3 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x3>;enable-method = "psci";next-level-cache = <&A53_L2>;};A53_L2: l2-cache0 {compatible = "cache";};- };
- memory@40000000 {
device_type = "memory";reg = <0x0 0x40000000 0 0x80000000>;- };
- clocks {
#address-cells = <1>;#size-cells = <0>;osc_32k: clock@0 {compatible = "fixed-clock";reg = <0>;#clock-cells = <0>;clock-frequency = <32768>;clock-output-names = "osc_32k";};osc_24m: clock@1 {compatible = "fixed-clock";reg = <1>;#clock-cells = <0>;clock-frequency = <24000000>;clock-output-names = "osc_24m";};clk_ext1: clock@2 {compatible = "fixed-clock";reg = <3>;#clock-cells = <0>;clock-frequency = <133000000>;clock-output-names = "clk_ext1";};clk_ext2: clock@3 {compatible = "fixed-clock";reg = <4>;#clock-cells = <0>;clock-frequency = <133000000>;clock-output-names = "clk_ext2";};clk_ext3: clock@4 {compatible = "fixed-clock";reg = <5>;#clock-cells = <0>;clock-frequency = <133000000>;clock-output-names = "clk_ext3";};clk_ext4: clock@5 {compatible = "fixed-clock";reg = <6>;#clock-cells = <0>;clock-frequency= <133000000>;clock-output-names = "clk_ext4";};- };
- gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";reg = <0x0 0x38800000 0 0x10000>, /* GICDist */
<0x0 0x38880000 0 0xC0000>; /* GICR(RD_base + SGI_base) */
#interrupt-cells = <3>;interrupt-controller;interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;- };
- psci {
compatible = "arm,psci-1.0";method = "smc";- };
- pmu {
compatible = "arm,armv8-pmuv3";interrupts = <GIC_PPI 7(GIC_CPU_MASK_SIMPLE(6) |IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>,<&A53_2>, <&A53_3>;
- };
- timer {
compatible = "arm,armv8-timer";interrupts = <GIC_PPI 13(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
<GIC_PPI 14(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
<GIC_PPI 11(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
clock-frequency = <8000000>;arm,no-tick-in-suspend;- };
- soc@0 {
compatible = "simple-bus";#address-cells = <2>;#size-cells = <2>;ranges;aips1: bus@30000000 {compatible = "fsl,aips-bus","simple-bus";
#address-cells = <2>;#size-cells = <2>;reg = <0x0 0x30000000 0x0 0x400000>;ranges;gpio1: gpio@30200000 {compatible ="fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x30200000 0x00x10000>;
interrupts = <GIC_SPI 64IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;};gpio2: gpio@30210000 {compatible ="fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x30210000 0x00x10000>;
interrupts = <GIC_SPI 66IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;};gpio3: gpio@30220000 {compatible ="fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x30220000 0x00x10000>;
interrupts = <GIC_SPI 68IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;};gpio4: gpio@30230000 {compatible ="fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x30230000 0x00x10000>;
interrupts = <GIC_SPI 70IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;};gpio5: gpio@30240000 {compatible ="fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x30240000 0x00x10000>;
interrupts = <GIC_SPI 72IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;#gpio-cells = <2>;interrupt-controller;#interrupt-cells = <2>;};wdog1: wdog@30280000 {compatible = "fsl,imx21-wdt";reg = <0 0x30280000 00x10000>;
interrupts = <GIC_SPI 78IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_WDOG1_ROOT>;
status = "disabled";};wdog2: wdog@30290000 {compatible = "fsl,imx21-wdt";reg = <0 0x30290000 00x10000>;
interrupts = <GIC_SPI 79IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_WDOG2_ROOT>;
status = "disabled";};wdog3: wdog@302a0000 {compatible = "fsl,imx21-wdt";reg = <0 0x302a0000 00x10000>;
interrupts = <GIC_SPI 10IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_WDOG3_ROOT>;
status = "disabled";};sdma2: dma-controller@302c0000 {compatible ="fsl,imx8mq-sdma", "fsl,imx7d-sdma";
reg = <0x0 0x302c0000 0x00x10000>;
interrupts = <GIC_SPI 103IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_SDMA2_ROOT>,
<&clkIMX8MM_CLK_SDMA2_ROOT>;
clock-names = "ipg", "ahb";#dma-cells = <3>;fsl,sdma-ram-script-name ="imx/sdma/sdma-imx7d.bin";
fsl,ratio-1-1;status = "okay";};sdma3: dma-controller@302b0000 {compatible ="fsl,imx8mq-sdma", "fsl,imx7d-sdma";
reg = <0x0 0x302b0000 0x00x10000>;
interrupts = <GIC_SPI 34IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_SDMA3_ROOT>,
<&clkIMX8MM_CLK_SDMA3_ROOT>;
clock-names = "ipg", "ahb";#dma-cells = <3>;fsl,sdma-ram-script-name ="imx/sdma/sdma-imx7d.bin";
fsl,ratio-1-1;status = "okay";};iomuxc: pinctrl@30330000 {compatible ="fsl,imx8mm-iomuxc";
reg = <0x0 0x30330000 0x00x10000>;
};gpr: iomuxc-gpr@30340000 {compatible ="fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x0 0x30340000 0x00x10000>;
};ocotp: ocotp-ctrl@30350000 {compatible ="fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
reg = <0 0x30350000 00x10000>;
clocks = <&clkIMX8MM_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */#address-cells = <1>;#size-cells = <1>;};anatop: anatop@30360000 {compatible ="fsl,imx8mm-anatop", "syscon", "simple-bus";
reg = <0x0 0x30360000 0x00x10000>;
};snvs: snvs@30370000 {compatible ="fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x0 0x30370000 0x00x10000>; +
snvs_rtc: snvs-rtc-lp{compatible ="fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;offset = <0x34>;interrupts = <GIC_SPI19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI20 IRQ_TYPE_LEVEL_HIGH>;
};snvs_pwrkey: snvs-powerkey {compatible ="fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;interrupts =<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode =<KEY_POWER>;
wakeup-source;};};clk: clock-controller@30380000 {compatible ="fsl,imx8mm-ccm";
reg = <0x0 0x30380000 0x00x10000>;
#clock-cells = <1>;clocks = <&osc_32k>,<&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>,<&clk_ext4>;
clock-names = "osc_32k","osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3","clk_ext4";
};src: src@30390000 {compatible ="fsl,imx8mm-src", "syscon";
reg = <0x0 0x30390000 0x00x10000>;
interrupts = <GIC_SPI 89IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;};gpc: gpc@303a0000 {compatible ="fsl,imx8mm-gpc", "syscon";
reg = <0x0 0x303a0000 0x00x10000>;
interrupt-controller;interrupts = <GIC_SPI 87IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;};};aips2: bus@30400000 {compatible = "fsl,aips-bus","simple-bus";
#address-cells = <2>;#size-cells = <2>;reg = <0x0 0x30400000 0x0 0x400000>;ranges;pwm1: pwm@30660000 {compatible ="fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x30660000 0x00x10000>;
interrupts = <GIC_SPI 81IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_PWM1_ROOT>,
<&clkIMX8MM_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";#pwm-cells = <2>;status = "disabled";};pwm2: pwm@30670000 {compatible ="fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x30670000 0x00x10000>;
interrupts = <GIC_SPI 82IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_PWM2_ROOT>,
<&clkIMX8MM_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";#pwm-cells = <2>;status = "disabled";};pwm3: pwm@30680000 {compatible ="fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x30680000 0x00x10000>;
interrupts = <GIC_SPI 83IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_PWM3_ROOT>,
<&clkIMX8MM_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";#pwm-cells = <2>;status = "disabled";};pwm4: pwm@30690000 {compatible ="fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x30690000 0x00x10000>;
interrupts = <GIC_SPI 84IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_PWM4_ROOT>,
<&clkIMX8MM_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";#pwm-cells = <2>;status = "disabled";};};aips3: bus@30800000 {compatible = "fsl,aips-bus","simple-bus";
#address-cells = <2>;#size-cells = <2>;reg = <0x0 0x30800000 0x0 0x400000>;ranges;ecspi1: ecspi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
reg = <0x0 0x30820000 0x00x10000>;
interrupts = <GIC_SPI 31IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_ECSPI1_ROOT>,
<&clkIMX8MM_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";status = "disabled";};ecspi2: ecspi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
reg = <0x0 0x30830000 0x00x10000>;
interrupts = <GIC_SPI 32IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_ECSPI2_ROOT>,
<&clkIMX8MM_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";status = "disabled";};ecspi3: ecspi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
reg = <0x0 0x30840000 0x00x10000>;
interrupts = <GIC_SPI 33IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_ECSPI3_ROOT>,
<&clkIMX8MM_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";status = "disabled";};uart1: serial@30860000 {compatible ="fsl,imx8mm-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x0 0x30860000 0x00x10000>;
interrupts = <GIC_SPI 26IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_UART1_ROOT>,
<&clkIMX8MM_CLK_UART1_ROOT>;
clock-names = "ipg", "per";status = "disabled";};uart3: serial@30880000 {compatible ="fsl,imx8mm-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x0 0x30880000 0x00x10000>;
interrupts = <GIC_SPI 28IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_UART3_ROOT>,
<&clkIMX8MM_CLK_UART3_ROOT>;
clock-names = "ipg", "per";status = "disabled";};uart2: serial@30890000 {compatible ="fsl,imx8mm-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x0 0x30890000 0x00x10000>;
interrupts = <GIC_SPI 27IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_UART2_ROOT>,
<&clkIMX8MM_CLK_UART2_ROOT>;
clock-names = "ipg", "per";status = "disabled";};i2c1: i2c@30a20000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-i2c", "fsl,imx21-i2c";
reg = <0x0 0x30a20000 0x00x10000>;
interrupts = <GIC_SPI 35IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_I2C1_ROOT>;
status = "disabled";};i2c2: i2c@30a30000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-i2c", "fsl,imx21-i2c";
reg = <0x0 0x30a30000 0x00x10000>;
interrupts = <GIC_SPI 36IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_I2C2_ROOT>;
status = "disabled";};i2c3: i2c@30a40000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-i2c", "fsl,imx21-i2c";
reg = <0x0 0x30a40000 0x00x10000>;
interrupts = <GIC_SPI 37IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_I2C3_ROOT>;
status = "disabled";};i2c4: i2c@30a50000 {#address-cells = <1>;#size-cells = <0>;compatible ="fsl,imx8mm-i2c", "fsl,imx21-i2c";
reg = <0x0 0x30a50000 0x00x10000>;
interrupts = <GIC_SPI 38IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_I2C4_ROOT>;
status = "disabled";};uart4: serial@30a60000 {compatible ="fsl,imx8mq-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x0 0x30a60000 0x00x10000>;
interrupts = <GIC_SPI 29IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_UART4_ROOT>,
<&clkIMX8MM_CLK_UART4_ROOT>;
clock-names = "ipg", "per";status = "disabled";};usdhc1: mmc@30b40000 {compatible ="fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
reg = <0x0 0x30b40000 0x00x10000>;
interrupts = <GIC_SPI 22IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_DUMMY>,
<&clkIMX8MM_CLK_NAND_USDHC_BUS>,
<&clkIMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb","per";
assigned-clocks = <&clkIMX8MM_CLK_USDHC1>;
assigned-clock-rates =<400000000>;
fsl,tuning-start-tap = <20>;fsl,tuning-step= <2>;bus-width = <4>;status = "disabled";};usdhc2: mmc@30b50000 {compatible ="fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
reg = <0x0 0x30b50000 0x00x10000>;
interrupts = <GIC_SPI 23IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_DUMMY>,
<&clkIMX8MM_CLK_NAND_USDHC_BUS>,
<&clkIMX8MM_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb","per";
fsl,tuning-start-tap = <20>;fsl,tuning-step= <2>;bus-width = <4>;status = "disabled";};usdhc3: mmc@30b60000 {compatible ="fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
reg = <0x0 0x30b60000 0x00x10000>;
interrupts = <GIC_SPI 24IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkIMX8MM_CLK_DUMMY>,
<&clkIMX8MM_CLK_NAND_USDHC_BUS>,
<&clkIMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb","per";
assigned-clocks = <&clkIMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates =<400000000>;
fsl,tuning-start-tap = <20>;fsl,tuning-step= <2>;bus-width = <4>;status = "disabled";};};- };
+}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 35c978e863..f520075875
100644
--- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK select IMX8MQ select IMX8M_LPDDR4
+config TARGET_IMX8MM_EVK
- bool "imx8mm LPDDR4 EVK board"
- select IMX8MM
- select SUPPORT_SPL
- select IMX8M_LPDDR4
Here you shall put the select DM_{UART,USDHC, etc}
endchoice
source "board/freescale/imx8mq_evk/Kconfig" +source "board/freescale/imx8mm_evk/Kconfig"
endif diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig new file mode 100644 index 0000000000..299691a619 --- /dev/null +++ b/board/freescale/imx8mm_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MM_EVK
+config SYS_BOARD
- default "imx8mm_evk"
+config SYS_VENDOR
- default "freescale"
+config SYS_CONFIG_NAME
- default "imx8mm_evk"
+endif diff --git a/board/freescale/imx8mm_evk/MAINTAINERS b/board/freescale/imx8mm_evk/MAINTAINERS new file mode 100644 index 0000000000..b031bb0674 --- /dev/null +++ b/board/freescale/imx8mm_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8MM EVK BOARD +M: Peng Fan peng.fan@nxp.com +S: Maintained +F: board/freescale/imx8mm_evk/ +F: include/configs/imx8mm_evk.h +F: configs/imx8mm_evk_defconfig diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile new file mode 100644 index 0000000000..1db7b62caf --- /dev/null +++ b/board/freescale/imx8mm_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += imx8mm_evk.o
+ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644 index 0000000000..a681aca04d --- /dev/null +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2018 NXP
- */
+#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <asm/arch/imx8mm_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/clock.h> +#include <spl.h> +#include <asm/mach-imx/dma.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX |
MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
+int board_early_init_f(void) +{
- struct wdog_regs *wdog = (struct wdog_regs
*)WDOG1_BASE_ADDR; +
- imx_iomux_v3_setup_multiple_pads(wdog_pads,
ARRAY_SIZE(wdog_pads)); +
- set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads,
ARRAY_SIZE(uart_pads)); +
- return 0;
+}
+#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{
- /* TODO */
- return 0;
+} +#endif
+int dram_init(void) +{
- /* rom_pointer[1] contains the size of TEE occupies
*/
- if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE -rom_pointer[1];
- else
gd->ram_size = PHYS_SDRAM_SIZE;- return 0;
+}
+#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd)
^^^ - fdt_board_setup ?
+{
- return 0;
+} +#endif
+#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const fec1_rst_pads[] = {
- IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 |
MUX_PAD_CTRL(NO_PAD_CTRL),
This shall be done with fsl_fec.c DM driver - there is support for adding reset pin (to dts).
+};
+static void setup_iomux_fec(void) +{
- imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads)); +
- gpio_request(FEC_RST_PAD, "fec1_rst");
- gpio_direction_output(FEC_RST_PAD, 0);
- udelay(500);
- gpio_direction_output(FEC_RST_PAD, 1);
+}
This shall be replaced with DM/DTS of the fsl_fec.c driver. Please also note that there are (at least on imx6q) some timing issues when we move the code to DM/DTS (some delay is needed).
+static int setup_fec(void) +{
- struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs*)IOMUXC_GPR_BASE_ADDR; +
- setup_iomux_fec();
- /* Use 125M anatop REF_CLK1 for ENET1, not from
external */
- clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
- return set_clk_enet(ENET_125MHZ);
+}
+int board_phy_config(struct phy_device *phydev) +{
- /* enable rgmii rxc skew and phy mode select to RGMII
copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
- if (phydev->drv->config)
phydev->drv->config(phydev);- return 0;
Which PHY do you use? E.g. KSZ... support passing those values via DTS.
+} +#endif
+int board_init(void) +{ +#ifdef CONFIG_FEC_MXC
- setup_fec();
+#endif
- return 0;
+}
+int board_mmc_get_env_dev(int devno) +{
- return devno - 1;
+}
+int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", "EVK");
- env_set("board_rev", "iMX8MM");
+#endif
- return 0;
+} diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644 index 0000000000..4bade5bf74 --- /dev/null +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -0,0 +1,1980 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2018 NXP
Author is missing.
- */
+#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h>
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
- /* Start to config, default 3200mbps */
- { DDRC_DBG1(0), 0x00000001 },
- { DDRC_PWRCTL(0), 0x00000001 },
- { DDRC_MSTR(0), 0xa1080020 },
- { DDRC_RFSHTMG(0), 0x005b00d2 },
- { DDRC_INIT0(0), 0xC003061B },
- { DDRC_INIT1(0), 0x009D0000 },
- { DDRC_INIT3(0), 0x00D4002D },
- { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
- { DDRC_INIT6(0), 0x0066004a },
- { DDRC_INIT7(0), 0x0006004a },
- { DDRC_DRAMTMG0(0), 0x1A201B22 },
- { DDRC_DRAMTMG1(0), 0x00060633 },
- { DDRC_DRAMTMG3(0), 0x00C0C000 },
- { DDRC_DRAMTMG4(0), 0x0F04080F },
- { DDRC_DRAMTMG5(0), 0x02040C0C },
- { DDRC_DRAMTMG6(0), 0x01010007 },
- { DDRC_DRAMTMG7(0), 0x00000401 },
- { DDRC_DRAMTMG12(0), 0x00020600 },
- { DDRC_DRAMTMG13(0), 0x0C100002 },
- { DDRC_DRAMTMG14(0), 0x000000E6 },
- { DDRC_DRAMTMG17(0), 0x00A00050 },
- { DDRC_ZQCTL0(0), 0x03200018 },
- { DDRC_ZQCTL1(0), 0x028061A8 },
- { DDRC_ZQCTL2(0), 0x00000000 },
- { DDRC_DFITMG0(0), 0x0497820A },
- { DDRC_DFITMG2(0), 0x0000170A },
- { DDRC_DRAMTMG2(0), 0x070E171a },
- { DDRC_DBICTL(0), 0x00000001 },
- { DDRC_DFITMG1(0), 0x00080303 },
- { DDRC_DFIUPD0(0), 0xE0400018 },
- { DDRC_DFIUPD1(0), 0x00DF00E4 },
- { DDRC_DFIUPD2(0), 0x80000000 },
- { DDRC_DFIMISC(0), 0x00000011 },
- { DDRC_DFIPHYMSTR(0), 0x00000000 },
- { DDRC_RANKCTL(0), 0x00000c99 },
- /* address mapping */
- { DDRC_ADDRMAP0(0), 0x0000001f },
- { DDRC_ADDRMAP1(0), 0x00080808 },
- { DDRC_ADDRMAP2(0), 0x00000000 },
- { DDRC_ADDRMAP3(0), 0x00000000 },
- { DDRC_ADDRMAP4(0), 0x00001f1f },
- { DDRC_ADDRMAP5(0), 0x07070707 },
- { DDRC_ADDRMAP6(0), 0x07070707 },
- { DDRC_ADDRMAP7(0), 0x00000f0f },
- /* performance setting */
- { DDRC_SCHED(0), 0x29001701 },
- { DDRC_SCHED1(0), 0x0000002c },
- { DDRC_PERFHPR1(0), 0x04000030 },
- { DDRC_PERFLPR1(0), 0x900093e7 },
- { DDRC_PERFWR1(0), 0x20005574 },
- { DDRC_PCCFG(0), 0x00000111 },
- { DDRC_PCFGW_0(0), 0x000072ff },
- { DDRC_PCFGQOS0_0(0), 0x02100e07 },
- { DDRC_PCFGQOS1_0(0), 0x00620096 },
- { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
- { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
- /* frequency P1&P2 */
- /* Frequency 1: 400mbps */
- { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
- { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
- { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
- { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
- { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
- { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
- { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
- { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
- { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
- { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
- { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
- { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
- { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
- { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
- { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
- { DDRC_FREQ1_INIT3(0), 0x00840000 },
- { DDRC_FREQ1_INIT4(0), 0x00310000 },
- { DDRC_FREQ1_INIT6(0), 0x0066004a },
- { DDRC_FREQ1_INIT7(0), 0x0006004a },
- /* Frequency 2: 100mbps */
- { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
- { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
- { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
- { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
- { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
- { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
- { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
- { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
- { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
- { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
- { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
- { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
- { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
- { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
- { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
- { DDRC_FREQ2_INIT3(0), 0x00840000 },
- { DDRC_FREQ2_INIT4(0), 0x00310008 },
- { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
- { DDRC_FREQ2_INIT6(0), 0x0066004a },
- { DDRC_FREQ2_INIT7(0), 0x0006004a },
- /* boot start point */
- { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
- { 0x1005f, 0x1ff },
- { 0x1015f, 0x1ff },
- { 0x1105f, 0x1ff },
- { 0x1115f, 0x1ff },
- { 0x1205f, 0x1ff },
- { 0x1215f, 0x1ff },
- { 0x1305f, 0x1ff },
- { 0x1315f, 0x1ff },
- { 0x11005f, 0x1ff },
- { 0x11015f, 0x1ff },
- { 0x11105f, 0x1ff },
- { 0x11115f, 0x1ff },
- { 0x11205f, 0x1ff },
- { 0x11215f, 0x1ff },
- { 0x11305f, 0x1ff },
- { 0x11315f, 0x1ff },
- { 0x21005f, 0x1ff },
- { 0x21015f, 0x1ff },
- { 0x21105f, 0x1ff },
- { 0x21115f, 0x1ff },
- { 0x21205f, 0x1ff },
- { 0x21215f, 0x1ff },
- { 0x21305f, 0x1ff },
- { 0x21315f, 0x1ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x3055, 0x1ff },
- { 0x4055, 0x1ff },
- { 0x5055, 0x1ff },
- { 0x6055, 0x1ff },
- { 0x7055, 0x1ff },
- { 0x8055, 0x1ff },
- { 0x9055, 0x1ff },
- { 0x200c5, 0x19 },
- { 0x1200c5, 0x7 },
- { 0x2200c5, 0x7 },
- { 0x2002e, 0x2 },
- { 0x12002e, 0x2 },
- { 0x22002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x20024, 0xab },
- { 0x2003a, 0x0 },
- { 0x120024, 0xab },
- { 0x2003a, 0x0 },
- { 0x220024, 0xab },
- { 0x2003a, 0x0 },
- { 0x20056, 0x3 },
- { 0x120056, 0xa },
- { 0x220056, 0xa },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x1204d, 0xe00 },
- { 0x1214d, 0xe00 },
- { 0x1304d, 0xe00 },
- { 0x1314d, 0xe00 },
- { 0x11004d, 0xe00 },
- { 0x11014d, 0xe00 },
- { 0x11104d, 0xe00 },
- { 0x11114d, 0xe00 },
- { 0x11204d, 0xe00 },
- { 0x11214d, 0xe00 },
- { 0x11304d, 0xe00 },
- { 0x11314d, 0xe00 },
- { 0x21004d, 0xe00 },
- { 0x21014d, 0xe00 },
- { 0x21104d, 0xe00 },
- { 0x21114d, 0xe00 },
- { 0x21204d, 0xe00 },
- { 0x21214d, 0xe00 },
- { 0x21304d, 0xe00 },
- { 0x21314d, 0xe00 },
- { 0x10049, 0xfbe },
- { 0x10149, 0xfbe },
- { 0x11049, 0xfbe },
- { 0x11149, 0xfbe },
- { 0x12049, 0xfbe },
- { 0x12149, 0xfbe },
- { 0x13049, 0xfbe },
- { 0x13149, 0xfbe },
- { 0x110049, 0xfbe },
- { 0x110149, 0xfbe },
- { 0x111049, 0xfbe },
- { 0x111149, 0xfbe },
- { 0x112049, 0xfbe },
- { 0x112149, 0xfbe },
- { 0x113049, 0xfbe },
- { 0x113149, 0xfbe },
- { 0x210049, 0xfbe },
- { 0x210149, 0xfbe },
- { 0x211049, 0xfbe },
- { 0x211149, 0xfbe },
- { 0x212049, 0xfbe },
- { 0x212149, 0xfbe },
- { 0x213049, 0xfbe },
- { 0x213149, 0xfbe },
- { 0x43, 0x63 },
- { 0x1043, 0x63 },
- { 0x2043, 0x63 },
- { 0x3043, 0x63 },
- { 0x4043, 0x63 },
- { 0x5043, 0x63 },
- { 0x6043, 0x63 },
- { 0x7043, 0x63 },
- { 0x8043, 0x63 },
- { 0x9043, 0x63 },
- { 0x20018, 0x3 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x20008, 0x2ee },
- { 0x120008, 0x64 },
- { 0x220008, 0x19 },
- { 0x20088, 0x9 },
- { 0x200b2, 0x1d4 },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x12043, 0x5a1 },
- { 0x12143, 0x5a1 },
- { 0x13043, 0x5a1 },
- { 0x13143, 0x5a1 },
- { 0x1200b2, 0xdc },
- { 0x110043, 0x5a1 },
- { 0x110143, 0x5a1 },
- { 0x111043, 0x5a1 },
- { 0x111143, 0x5a1 },
- { 0x112043, 0x5a1 },
- { 0x112143, 0x5a1 },
- { 0x113043, 0x5a1 },
- { 0x113143, 0x5a1 },
- { 0x2200b2, 0xdc },
- { 0x210043, 0x5a1 },
- { 0x210143, 0x5a1 },
- { 0x211043, 0x5a1 },
- { 0x211143, 0x5a1 },
- { 0x212043, 0x5a1 },
- { 0x212143, 0x5a1 },
- { 0x213043, 0x5a1 },
- { 0x213143, 0x5a1 },
- { 0x200fa, 0x1 },
- { 0x1200fa, 0x1 },
- { 0x2200fa, 0x1 },
- { 0x20019, 0x1 },
- { 0x120019, 0x1 },
- { 0x220019, 0x1 },
- { 0x200f0, 0x660 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x4444 },
- { 0x200f3, 0x8888 },
- { 0x200f4, 0x5665 },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x20025, 0x0 },
- { 0x2002d, LPDDR4_PHY_DMIPinPresent },
- { 0x12002d, LPDDR4_PHY_DMIPinPresent },
- { 0x22002d, LPDDR4_PHY_DMIPinPresent },
- { 0x200c7, 0x21 },
- { 0x200ca, 0x24 },
- { 0x1200c7, 0x21 },
- { 0x1200ca, 0x24 },
- { 0x2200c7, 0x21 },
- { 0x2200ca, 0x24 },
Why do you add tuple - offset and value? Shouldn't we have the DDR training functions here?
It is possible to train IMX6Q and Vybrid's DDR3 (as fair as I know). Would it be also possible to add the DDR4 training code for IMX8?
+};
+/* ddr phy trained csr */ +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
- { 0x200b2, 0x0 },
- { 0x1200b2, 0x0 },
- { 0x2200b2, 0x0 },
- { 0x200cb, 0x0 },
- { 0x10043, 0x0 },
- { 0x110043, 0x0 },
- { 0x210043, 0x0 },
- { 0x10143, 0x0 },
- { 0x110143, 0x0 },
- { 0x210143, 0x0 },
- { 0x11043, 0x0 },
- { 0x111043, 0x0 },
- { 0x211043, 0x0 },
- { 0x11143, 0x0 },
- { 0x111143, 0x0 },
- { 0x211143, 0x0 },
- { 0x12043, 0x0 },
- { 0x112043, 0x0 },
- { 0x212043, 0x0 },
- { 0x12143, 0x0 },
- { 0x112143, 0x0 },
- { 0x212143, 0x0 },
- { 0x13043, 0x0 },
- { 0x113043, 0x0 },
- { 0x213043, 0x0 },
- { 0x13143, 0x0 },
- { 0x113143, 0x0 },
- { 0x213143, 0x0 },
- { 0x80, 0x0 },
- { 0x100080, 0x0 },
- { 0x200080, 0x0 },
- { 0x1080, 0x0 },
- { 0x101080, 0x0 },
- { 0x201080, 0x0 },
- { 0x2080, 0x0 },
- { 0x102080, 0x0 },
- { 0x202080, 0x0 },
- { 0x3080, 0x0 },
- { 0x103080, 0x0 },
- { 0x203080, 0x0 },
- { 0x4080, 0x0 },
- { 0x104080, 0x0 },
- { 0x204080, 0x0 },
- { 0x5080, 0x0 },
- { 0x105080, 0x0 },
- { 0x205080, 0x0 },
- { 0x6080, 0x0 },
- { 0x106080, 0x0 },
- { 0x206080, 0x0 },
- { 0x7080, 0x0 },
- { 0x107080, 0x0 },
- { 0x207080, 0x0 },
- { 0x8080, 0x0 },
- { 0x108080, 0x0 },
- { 0x208080, 0x0 },
- { 0x9080, 0x0 },
- { 0x109080, 0x0 },
- { 0x209080, 0x0 },
- { 0x10080, 0x0 },
- { 0x110080, 0x0 },
- { 0x210080, 0x0 },
- { 0x10180, 0x0 },
- { 0x110180, 0x0 },
- { 0x210180, 0x0 },
- { 0x11080, 0x0 },
- { 0x111080, 0x0 },
- { 0x211080, 0x0 },
- { 0x11180, 0x0 },
- { 0x111180, 0x0 },
- { 0x211180, 0x0 },
- { 0x12080, 0x0 },
- { 0x112080, 0x0 },
- { 0x212080, 0x0 },
- { 0x12180, 0x0 },
- { 0x112180, 0x0 },
- { 0x212180, 0x0 },
- { 0x13080, 0x0 },
- { 0x113080, 0x0 },
- { 0x213080, 0x0 },
- { 0x13180, 0x0 },
- { 0x113180, 0x0 },
- { 0x213180, 0x0 },
- { 0x10081, 0x0 },
- { 0x110081, 0x0 },
- { 0x210081, 0x0 },
- { 0x10181, 0x0 },
- { 0x110181, 0x0 },
- { 0x210181, 0x0 },
- { 0x11081, 0x0 },
- { 0x111081, 0x0 },
- { 0x211081, 0x0 },
- { 0x11181, 0x0 },
- { 0x111181, 0x0 },
- { 0x211181, 0x0 },
- { 0x12081, 0x0 },
- { 0x112081, 0x0 },
- { 0x212081, 0x0 },
- { 0x12181, 0x0 },
- { 0x112181, 0x0 },
- { 0x212181, 0x0 },
- { 0x13081, 0x0 },
- { 0x113081, 0x0 },
- { 0x213081, 0x0 },
- { 0x13181, 0x0 },
- { 0x113181, 0x0 },
- { 0x213181, 0x0 },
- { 0x100d0, 0x0 },
- { 0x1100d0, 0x0 },
- { 0x2100d0, 0x0 },
- { 0x101d0, 0x0 },
- { 0x1101d0, 0x0 },
- { 0x2101d0, 0x0 },
- { 0x110d0, 0x0 },
- { 0x1110d0, 0x0 },
- { 0x2110d0, 0x0 },
- { 0x111d0, 0x0 },
- { 0x1111d0, 0x0 },
- { 0x2111d0, 0x0 },
- { 0x120d0, 0x0 },
- { 0x1120d0, 0x0 },
- { 0x2120d0, 0x0 },
- { 0x121d0, 0x0 },
- { 0x1121d0, 0x0 },
- { 0x2121d0, 0x0 },
- { 0x130d0, 0x0 },
- { 0x1130d0, 0x0 },
- { 0x2130d0, 0x0 },
- { 0x131d0, 0x0 },
- { 0x1131d0, 0x0 },
- { 0x2131d0, 0x0 },
- { 0x100d1, 0x0 },
- { 0x1100d1, 0x0 },
- { 0x2100d1, 0x0 },
- { 0x101d1, 0x0 },
- { 0x1101d1, 0x0 },
- { 0x2101d1, 0x0 },
- { 0x110d1, 0x0 },
- { 0x1110d1, 0x0 },
- { 0x2110d1, 0x0 },
- { 0x111d1, 0x0 },
- { 0x1111d1, 0x0 },
- { 0x2111d1, 0x0 },
- { 0x120d1, 0x0 },
- { 0x1120d1, 0x0 },
- { 0x2120d1, 0x0 },
- { 0x121d1, 0x0 },
- { 0x1121d1, 0x0 },
- { 0x2121d1, 0x0 },
- { 0x130d1, 0x0 },
- { 0x1130d1, 0x0 },
- { 0x2130d1, 0x0 },
- { 0x131d1, 0x0 },
- { 0x1131d1, 0x0 },
- { 0x2131d1, 0x0 },
- { 0x10068, 0x0 },
- { 0x10168, 0x0 },
- { 0x10268, 0x0 },
- { 0x10368, 0x0 },
- { 0x10468, 0x0 },
- { 0x10568, 0x0 },
- { 0x10668, 0x0 },
- { 0x10768, 0x0 },
- { 0x10868, 0x0 },
- { 0x11068, 0x0 },
- { 0x11168, 0x0 },
- { 0x11268, 0x0 },
- { 0x11368, 0x0 },
- { 0x11468, 0x0 },
- { 0x11568, 0x0 },
- { 0x11668, 0x0 },
- { 0x11768, 0x0 },
- { 0x11868, 0x0 },
- { 0x12068, 0x0 },
- { 0x12168, 0x0 },
- { 0x12268, 0x0 },
- { 0x12368, 0x0 },
- { 0x12468, 0x0 },
- { 0x12568, 0x0 },
- { 0x12668, 0x0 },
- { 0x12768, 0x0 },
- { 0x12868, 0x0 },
- { 0x13068, 0x0 },
- { 0x13168, 0x0 },
- { 0x13268, 0x0 },
- { 0x13368, 0x0 },
- { 0x13468, 0x0 },
- { 0x13568, 0x0 },
- { 0x13668, 0x0 },
- { 0x13768, 0x0 },
- { 0x13868, 0x0 },
- { 0x10069, 0x0 },
- { 0x10169, 0x0 },
- { 0x10269, 0x0 },
- { 0x10369, 0x0 },
- { 0x10469, 0x0 },
- { 0x10569, 0x0 },
- { 0x10669, 0x0 },
- { 0x10769, 0x0 },
- { 0x10869, 0x0 },
- { 0x11069, 0x0 },
- { 0x11169, 0x0 },
- { 0x11269, 0x0 },
- { 0x11369, 0x0 },
- { 0x11469, 0x0 },
- { 0x11569, 0x0 },
- { 0x11669, 0x0 },
- { 0x11769, 0x0 },
- { 0x11869, 0x0 },
- { 0x12069, 0x0 },
- { 0x12169, 0x0 },
- { 0x12269, 0x0 },
- { 0x12369, 0x0 },
- { 0x12469, 0x0 },
- { 0x12569, 0x0 },
- { 0x12669, 0x0 },
- { 0x12769, 0x0 },
- { 0x12869, 0x0 },
- { 0x13069, 0x0 },
- { 0x13169, 0x0 },
- { 0x13269, 0x0 },
- { 0x13369, 0x0 },
- { 0x13469, 0x0 },
- { 0x13569, 0x0 },
- { 0x13669, 0x0 },
- { 0x13769, 0x0 },
- { 0x13869, 0x0 },
- { 0x1008c, 0x0 },
- { 0x11008c, 0x0 },
- { 0x21008c, 0x0 },
- { 0x1018c, 0x0 },
- { 0x11018c, 0x0 },
- { 0x21018c, 0x0 },
- { 0x1108c, 0x0 },
- { 0x11108c, 0x0 },
- { 0x21108c, 0x0 },
- { 0x1118c, 0x0 },
- { 0x11118c, 0x0 },
- { 0x21118c, 0x0 },
- { 0x1208c, 0x0 },
- { 0x11208c, 0x0 },
- { 0x21208c, 0x0 },
- { 0x1218c, 0x0 },
- { 0x11218c, 0x0 },
- { 0x21218c, 0x0 },
- { 0x1308c, 0x0 },
- { 0x11308c, 0x0 },
- { 0x21308c, 0x0 },
- { 0x1318c, 0x0 },
- { 0x11318c, 0x0 },
- { 0x21318c, 0x0 },
- { 0x1008d, 0x0 },
- { 0x11008d, 0x0 },
- { 0x21008d, 0x0 },
- { 0x1018d, 0x0 },
- { 0x11018d, 0x0 },
- { 0x21018d, 0x0 },
- { 0x1108d, 0x0 },
- { 0x11108d, 0x0 },
- { 0x21108d, 0x0 },
- { 0x1118d, 0x0 },
- { 0x11118d, 0x0 },
- { 0x21118d, 0x0 },
- { 0x1208d, 0x0 },
- { 0x11208d, 0x0 },
- { 0x21208d, 0x0 },
- { 0x1218d, 0x0 },
- { 0x11218d, 0x0 },
- { 0x21218d, 0x0 },
- { 0x1308d, 0x0 },
- { 0x11308d, 0x0 },
- { 0x21308d, 0x0 },
- { 0x1318d, 0x0 },
- { 0x11318d, 0x0 },
- { 0x21318d, 0x0 },
- { 0x100c0, 0x0 },
- { 0x1100c0, 0x0 },
- { 0x2100c0, 0x0 },
- { 0x101c0, 0x0 },
- { 0x1101c0, 0x0 },
- { 0x2101c0, 0x0 },
- { 0x102c0, 0x0 },
- { 0x1102c0, 0x0 },
- { 0x2102c0, 0x0 },
- { 0x103c0, 0x0 },
- { 0x1103c0, 0x0 },
- { 0x2103c0, 0x0 },
- { 0x104c0, 0x0 },
- { 0x1104c0, 0x0 },
- { 0x2104c0, 0x0 },
- { 0x105c0, 0x0 },
- { 0x1105c0, 0x0 },
- { 0x2105c0, 0x0 },
- { 0x106c0, 0x0 },
- { 0x1106c0, 0x0 },
- { 0x2106c0, 0x0 },
- { 0x107c0, 0x0 },
- { 0x1107c0, 0x0 },
- { 0x2107c0, 0x0 },
- { 0x108c0, 0x0 },
- { 0x1108c0, 0x0 },
- { 0x2108c0, 0x0 },
- { 0x110c0, 0x0 },
- { 0x1110c0, 0x0 },
- { 0x2110c0, 0x0 },
- { 0x111c0, 0x0 },
- { 0x1111c0, 0x0 },
- { 0x2111c0, 0x0 },
- { 0x112c0, 0x0 },
- { 0x1112c0, 0x0 },
- { 0x2112c0, 0x0 },
- { 0x113c0, 0x0 },
- { 0x1113c0, 0x0 },
- { 0x2113c0, 0x0 },
- { 0x114c0, 0x0 },
- { 0x1114c0, 0x0 },
- { 0x2114c0, 0x0 },
- { 0x115c0, 0x0 },
- { 0x1115c0, 0x0 },
- { 0x2115c0, 0x0 },
- { 0x116c0, 0x0 },
- { 0x1116c0, 0x0 },
- { 0x2116c0, 0x0 },
- { 0x117c0, 0x0 },
- { 0x1117c0, 0x0 },
- { 0x2117c0, 0x0 },
- { 0x118c0, 0x0 },
- { 0x1118c0, 0x0 },
- { 0x2118c0, 0x0 },
- { 0x120c0, 0x0 },
- { 0x1120c0, 0x0 },
- { 0x2120c0, 0x0 },
- { 0x121c0, 0x0 },
- { 0x1121c0, 0x0 },
- { 0x2121c0, 0x0 },
- { 0x122c0, 0x0 },
- { 0x1122c0, 0x0 },
- { 0x2122c0, 0x0 },
- { 0x123c0, 0x0 },
- { 0x1123c0, 0x0 },
- { 0x2123c0, 0x0 },
- { 0x124c0, 0x0 },
- { 0x1124c0, 0x0 },
- { 0x2124c0, 0x0 },
- { 0x125c0, 0x0 },
- { 0x1125c0, 0x0 },
- { 0x2125c0, 0x0 },
- { 0x126c0, 0x0 },
- { 0x1126c0, 0x0 },
- { 0x2126c0, 0x0 },
- { 0x127c0, 0x0 },
- { 0x1127c0, 0x0 },
- { 0x2127c0, 0x0 },
- { 0x128c0, 0x0 },
- { 0x1128c0, 0x0 },
- { 0x2128c0, 0x0 },
- { 0x130c0, 0x0 },
- { 0x1130c0, 0x0 },
- { 0x2130c0, 0x0 },
- { 0x131c0, 0x0 },
- { 0x1131c0, 0x0 },
- { 0x2131c0, 0x0 },
- { 0x132c0, 0x0 },
- { 0x1132c0, 0x0 },
- { 0x2132c0, 0x0 },
- { 0x133c0, 0x0 },
- { 0x1133c0, 0x0 },
- { 0x2133c0, 0x0 },
- { 0x134c0, 0x0 },
- { 0x1134c0, 0x0 },
- { 0x2134c0, 0x0 },
- { 0x135c0, 0x0 },
- { 0x1135c0, 0x0 },
- { 0x2135c0, 0x0 },
- { 0x136c0, 0x0 },
- { 0x1136c0, 0x0 },
- { 0x2136c0, 0x0 },
- { 0x137c0, 0x0 },
- { 0x1137c0, 0x0 },
- { 0x2137c0, 0x0 },
- { 0x138c0, 0x0 },
- { 0x1138c0, 0x0 },
- { 0x2138c0, 0x0 },
- { 0x100c1, 0x0 },
- { 0x1100c1, 0x0 },
- { 0x2100c1, 0x0 },
- { 0x101c1, 0x0 },
- { 0x1101c1, 0x0 },
- { 0x2101c1, 0x0 },
- { 0x102c1, 0x0 },
- { 0x1102c1, 0x0 },
- { 0x2102c1, 0x0 },
- { 0x103c1, 0x0 },
- { 0x1103c1, 0x0 },
- { 0x2103c1, 0x0 },
- { 0x104c1, 0x0 },
- { 0x1104c1, 0x0 },
- { 0x2104c1, 0x0 },
- { 0x105c1, 0x0 },
- { 0x1105c1, 0x0 },
- { 0x2105c1, 0x0 },
- { 0x106c1, 0x0 },
- { 0x1106c1, 0x0 },
- { 0x2106c1, 0x0 },
- { 0x107c1, 0x0 },
- { 0x1107c1, 0x0 },
- { 0x2107c1, 0x0 },
- { 0x108c1, 0x0 },
- { 0x1108c1, 0x0 },
- { 0x2108c1, 0x0 },
- { 0x110c1, 0x0 },
- { 0x1110c1, 0x0 },
- { 0x2110c1, 0x0 },
- { 0x111c1, 0x0 },
- { 0x1111c1, 0x0 },
- { 0x2111c1, 0x0 },
- { 0x112c1, 0x0 },
- { 0x1112c1, 0x0 },
- { 0x2112c1, 0x0 },
- { 0x113c1, 0x0 },
- { 0x1113c1, 0x0 },
- { 0x2113c1, 0x0 },
- { 0x114c1, 0x0 },
- { 0x1114c1, 0x0 },
- { 0x2114c1, 0x0 },
- { 0x115c1, 0x0 },
- { 0x1115c1, 0x0 },
- { 0x2115c1, 0x0 },
- { 0x116c1, 0x0 },
- { 0x1116c1, 0x0 },
- { 0x2116c1, 0x0 },
- { 0x117c1, 0x0 },
- { 0x1117c1, 0x0 },
- { 0x2117c1, 0x0 },
- { 0x118c1, 0x0 },
- { 0x1118c1, 0x0 },
- { 0x2118c1, 0x0 },
- { 0x120c1, 0x0 },
- { 0x1120c1, 0x0 },
- { 0x2120c1, 0x0 },
- { 0x121c1, 0x0 },
- { 0x1121c1, 0x0 },
- { 0x2121c1, 0x0 },
- { 0x122c1, 0x0 },
- { 0x1122c1, 0x0 },
- { 0x2122c1, 0x0 },
- { 0x123c1, 0x0 },
- { 0x1123c1, 0x0 },
- { 0x2123c1, 0x0 },
- { 0x124c1, 0x0 },
- { 0x1124c1, 0x0 },
- { 0x2124c1, 0x0 },
- { 0x125c1, 0x0 },
- { 0x1125c1, 0x0 },
- { 0x2125c1, 0x0 },
- { 0x126c1, 0x0 },
- { 0x1126c1, 0x0 },
- { 0x2126c1, 0x0 },
- { 0x127c1, 0x0 },
- { 0x1127c1, 0x0 },
- { 0x2127c1, 0x0 },
- { 0x128c1, 0x0 },
- { 0x1128c1, 0x0 },
- { 0x2128c1, 0x0 },
- { 0x130c1, 0x0 },
- { 0x1130c1, 0x0 },
- { 0x2130c1, 0x0 },
- { 0x131c1, 0x0 },
- { 0x1131c1, 0x0 },
- { 0x2131c1, 0x0 },
- { 0x132c1, 0x0 },
- { 0x1132c1, 0x0 },
- { 0x2132c1, 0x0 },
- { 0x133c1, 0x0 },
- { 0x1133c1, 0x0 },
- { 0x2133c1, 0x0 },
- { 0x134c1, 0x0 },
- { 0x1134c1, 0x0 },
- { 0x2134c1, 0x0 },
- { 0x135c1, 0x0 },
- { 0x1135c1, 0x0 },
- { 0x2135c1, 0x0 },
- { 0x136c1, 0x0 },
- { 0x1136c1, 0x0 },
- { 0x2136c1, 0x0 },
- { 0x137c1, 0x0 },
- { 0x1137c1, 0x0 },
- { 0x2137c1, 0x0 },
- { 0x138c1, 0x0 },
- { 0x1138c1, 0x0 },
- { 0x2138c1, 0x0 },
- { 0x10020, 0x0 },
- { 0x110020, 0x0 },
- { 0x210020, 0x0 },
- { 0x11020, 0x0 },
- { 0x111020, 0x0 },
- { 0x211020, 0x0 },
- { 0x12020, 0x0 },
- { 0x112020, 0x0 },
- { 0x212020, 0x0 },
- { 0x13020, 0x0 },
- { 0x113020, 0x0 },
- { 0x213020, 0x0 },
- { 0x20072, 0x0 },
- { 0x20073, 0x0 },
- { 0x20074, 0x0 },
- { 0x100aa, 0x0 },
- { 0x110aa, 0x0 },
- { 0x120aa, 0x0 },
- { 0x130aa, 0x0 },
- { 0x20010, 0x0 },
- { 0x120010, 0x0 },
- { 0x220010, 0x0 },
- { 0x20011, 0x0 },
- { 0x120011, 0x0 },
- { 0x220011, 0x0 },
- { 0x100ae, 0x0 },
- { 0x1100ae, 0x0 },
- { 0x2100ae, 0x0 },
- { 0x100af, 0x0 },
- { 0x1100af, 0x0 },
- { 0x2100af, 0x0 },
- { 0x110ae, 0x0 },
- { 0x1110ae, 0x0 },
- { 0x2110ae, 0x0 },
- { 0x110af, 0x0 },
- { 0x1110af, 0x0 },
- { 0x2110af, 0x0 },
- { 0x120ae, 0x0 },
- { 0x1120ae, 0x0 },
- { 0x2120ae, 0x0 },
- { 0x120af, 0x0 },
- { 0x1120af, 0x0 },
- { 0x2120af, 0x0 },
- { 0x130ae, 0x0 },
- { 0x1130ae, 0x0 },
- { 0x2130ae, 0x0 },
- { 0x130af, 0x0 },
- { 0x1130af, 0x0 },
- { 0x2130af, 0x0 },
- { 0x20020, 0x0 },
- { 0x120020, 0x0 },
- { 0x220020, 0x0 },
- { 0x100a0, 0x0 },
- { 0x100a1, 0x0 },
- { 0x100a2, 0x0 },
- { 0x100a3, 0x0 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x0 },
- { 0x100a6, 0x0 },
- { 0x100a7, 0x0 },
- { 0x110a0, 0x0 },
- { 0x110a1, 0x0 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x0 },
- { 0x110a4, 0x0 },
- { 0x110a5, 0x0 },
- { 0x110a6, 0x0 },
- { 0x110a7, 0x0 },
- { 0x120a0, 0x0 },
- { 0x120a1, 0x0 },
- { 0x120a2, 0x0 },
- { 0x120a3, 0x0 },
- { 0x120a4, 0x0 },
- { 0x120a5, 0x0 },
- { 0x120a6, 0x0 },
- { 0x120a7, 0x0 },
- { 0x130a0, 0x0 },
- { 0x130a1, 0x0 },
- { 0x130a2, 0x0 },
- { 0x130a3, 0x0 },
- { 0x130a4, 0x0 },
- { 0x130a5, 0x0 },
- { 0x130a6, 0x0 },
- { 0x130a7, 0x0 },
- { 0x2007c, 0x0 },
- { 0x12007c, 0x0 },
- { 0x22007c, 0x0 },
- { 0x2007d, 0x0 },
- { 0x12007d, 0x0 },
- { 0x22007d, 0x0 },
- { 0x400fd, 0x0 },
- { 0x400c0, 0x0 },
- { 0x90201, 0x0 },
- { 0x190201, 0x0 },
- { 0x290201, 0x0 },
- { 0x90202, 0x0 },
- { 0x190202, 0x0 },
- { 0x290202, 0x0 },
- { 0x90203, 0x0 },
- { 0x190203, 0x0 },
- { 0x290203, 0x0 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x90205, 0x0 },
- { 0x190205, 0x0 },
- { 0x290205, 0x0 },
- { 0x90206, 0x0 },
- { 0x190206, 0x0 },
- { 0x290206, 0x0 },
- { 0x90207, 0x0 },
- { 0x190207, 0x0 },
- { 0x290207, 0x0 },
- { 0x90208, 0x0 },
- { 0x190208, 0x0 },
- { 0x290208, 0x0 },
- { 0x10062, 0x0 },
- { 0x10162, 0x0 },
- { 0x10262, 0x0 },
- { 0x10362, 0x0 },
- { 0x10462, 0x0 },
- { 0x10562, 0x0 },
- { 0x10662, 0x0 },
- { 0x10762, 0x0 },
- { 0x10862, 0x0 },
- { 0x11062, 0x0 },
- { 0x11162, 0x0 },
- { 0x11262, 0x0 },
- { 0x11362, 0x0 },
- { 0x11462, 0x0 },
- { 0x11562, 0x0 },
- { 0x11662, 0x0 },
- { 0x11762, 0x0 },
- { 0x11862, 0x0 },
- { 0x12062, 0x0 },
- { 0x12162, 0x0 },
- { 0x12262, 0x0 },
- { 0x12362, 0x0 },
- { 0x12462, 0x0 },
- { 0x12562, 0x0 },
- { 0x12662, 0x0 },
- { 0x12762, 0x0 },
- { 0x12862, 0x0 },
- { 0x13062, 0x0 },
- { 0x13162, 0x0 },
- { 0x13262, 0x0 },
- { 0x13362, 0x0 },
- { 0x13462, 0x0 },
- { 0x13562, 0x0 },
- { 0x13662, 0x0 },
- { 0x13762, 0x0 },
- { 0x13862, 0x0 },
- { 0x20077, 0x0 },
- { 0x10001, 0x0 },
- { 0x11001, 0x0 },
- { 0x12001, 0x0 },
- { 0x13001, 0x0 },
- { 0x10040, 0x0 },
- { 0x10140, 0x0 },
- { 0x10240, 0x0 },
- { 0x10340, 0x0 },
- { 0x10440, 0x0 },
- { 0x10540, 0x0 },
- { 0x10640, 0x0 },
- { 0x10740, 0x0 },
- { 0x10840, 0x0 },
- { 0x10030, 0x0 },
- { 0x10130, 0x0 },
- { 0x10230, 0x0 },
- { 0x10330, 0x0 },
- { 0x10430, 0x0 },
- { 0x10530, 0x0 },
- { 0x10630, 0x0 },
- { 0x10730, 0x0 },
- { 0x10830, 0x0 },
- { 0x11040, 0x0 },
- { 0x11140, 0x0 },
- { 0x11240, 0x0 },
- { 0x11340, 0x0 },
- { 0x11440, 0x0 },
- { 0x11540, 0x0 },
- { 0x11640, 0x0 },
- { 0x11740, 0x0 },
- { 0x11840, 0x0 },
- { 0x11030, 0x0 },
- { 0x11130, 0x0 },
- { 0x11230, 0x0 },
- { 0x11330, 0x0 },
- { 0x11430, 0x0 },
- { 0x11530, 0x0 },
- { 0x11630, 0x0 },
- { 0x11730, 0x0 },
- { 0x11830, 0x0 },
- { 0x12040, 0x0 },
- { 0x12140, 0x0 },
- { 0x12240, 0x0 },
- { 0x12340, 0x0 },
- { 0x12440, 0x0 },
- { 0x12540, 0x0 },
- { 0x12640, 0x0 },
- { 0x12740, 0x0 },
- { 0x12840, 0x0 },
- { 0x12030, 0x0 },
- { 0x12130, 0x0 },
- { 0x12230, 0x0 },
- { 0x12330, 0x0 },
- { 0x12430, 0x0 },
- { 0x12530, 0x0 },
- { 0x12630, 0x0 },
- { 0x12730, 0x0 },
- { 0x12830, 0x0 },
- { 0x13040, 0x0 },
- { 0x13140, 0x0 },
- { 0x13240, 0x0 },
- { 0x13340, 0x0 },
- { 0x13440, 0x0 },
- { 0x13540, 0x0 },
- { 0x13640, 0x0 },
- { 0x13740, 0x0 },
- { 0x13840, 0x0 },
- { 0x13030, 0x0 },
- { 0x13130, 0x0 },
- { 0x13230, 0x0 },
- { 0x13330, 0x0 },
- { 0x13430, 0x0 },
- { 0x13530, 0x0 },
- { 0x13630, 0x0 },
- { 0x13730, 0x0 },
- { 0x13830, 0x0 },
+};
The same as above. Please look into imx6q DDR3 training code.
+/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
- { 0x54003, 0xbb8 },
- { 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) |
LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
- { 0x54008, 0x131f },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
- { 0x5401f, 0x2dd4 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0xd400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
- { 0x54034, 0x6600 },
- { 0x54035, 0x84d },
- { 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
- { 0x54038, 0xd400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
- { 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
+};
+/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x101 },
- { 0x54003, 0x190 },
- { 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) |
LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x84 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
- { 0x5401f, 0x84 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0x8400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
- { 0x54034, 0x6600 },
- { 0x54035, 0x84d },
- { 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
- { 0x54038, 0x8400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
- { 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
+};
+/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x102 },
- { 0x54003, 0x64 },
- { 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) |
LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x84 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
- { 0x5401f, 0x84 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0x8400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
- { 0x54034, 0x6600 },
- { 0x54035, 0x84d },
- { 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
- { 0x54038, 0x8400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
- { 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
+};
+/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
- { 0x54003, 0xbb8 },
- { 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) |
LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
- { 0x54008, 0x61 },
- { 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
- { 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x100 },
- { 0x54010, 0x1f7f },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
- { 0x54019, 0x2dd4 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
- { 0x5401f, 0x2dd4 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
- { 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
- { 0x54032, 0xd400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
- { 0x54034, 0x6600 },
- { 0x54035, 0x84d },
- { 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
- { 0x54038, 0xd400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
- { 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
- { 0xd0000, 0x1 },
+};
+/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = {
- { 0xd0000, 0x0 },
- { 0x90000, 0x10 },
- { 0x90001, 0x400 },
- { 0x90002, 0x10e },
- { 0x90003, 0x0 },
- { 0x90004, 0x0 },
- { 0x90005, 0x8 },
- { 0x90029, 0xb },
- { 0x9002a, 0x480 },
- { 0x9002b, 0x109 },
- { 0x9002c, 0x8 },
- { 0x9002d, 0x448 },
- { 0x9002e, 0x139 },
- { 0x9002f, 0x8 },
- { 0x90030, 0x478 },
- { 0x90031, 0x109 },
- { 0x90032, 0x0 },
- { 0x90033, 0xe8 },
- { 0x90034, 0x109 },
- { 0x90035, 0x2 },
- { 0x90036, 0x10 },
- { 0x90037, 0x139 },
- { 0x90038, 0xf },
- { 0x90039, 0x7c0 },
- { 0x9003a, 0x139 },
- { 0x9003b, 0x44 },
- { 0x9003c, 0x630 },
- { 0x9003d, 0x159 },
- { 0x9003e, 0x14f },
- { 0x9003f, 0x630 },
- { 0x90040, 0x159 },
- { 0x90041, 0x47 },
- { 0x90042, 0x630 },
- { 0x90043, 0x149 },
- { 0x90044, 0x4f },
- { 0x90045, 0x630 },
- { 0x90046, 0x179 },
- { 0x90047, 0x8 },
- { 0x90048, 0xe0 },
- { 0x90049, 0x109 },
- { 0x9004a, 0x0 },
- { 0x9004b, 0x7c8 },
- { 0x9004c, 0x109 },
- { 0x9004d, 0x0 },
- { 0x9004e, 0x1 },
- { 0x9004f, 0x8 },
- { 0x90050, 0x0 },
- { 0x90051, 0x45a },
- { 0x90052, 0x9 },
- { 0x90053, 0x0 },
- { 0x90054, 0x448 },
- { 0x90055, 0x109 },
- { 0x90056, 0x40 },
- { 0x90057, 0x630 },
- { 0x90058, 0x179 },
- { 0x90059, 0x1 },
- { 0x9005a, 0x618 },
- { 0x9005b, 0x109 },
- { 0x9005c, 0x40c0 },
- { 0x9005d, 0x630 },
- { 0x9005e, 0x149 },
- { 0x9005f, 0x8 },
- { 0x90060, 0x4 },
- { 0x90061, 0x48 },
- { 0x90062, 0x4040 },
- { 0x90063, 0x630 },
- { 0x90064, 0x149 },
- { 0x90065, 0x0 },
- { 0x90066, 0x4 },
- { 0x90067, 0x48 },
- { 0x90068, 0x40 },
- { 0x90069, 0x630 },
- { 0x9006a, 0x149 },
- { 0x9006b, 0x10 },
- { 0x9006c, 0x4 },
- { 0x9006d, 0x18 },
- { 0x9006e, 0x0 },
- { 0x9006f, 0x4 },
- { 0x90070, 0x78 },
- { 0x90071, 0x549 },
- { 0x90072, 0x630 },
- { 0x90073, 0x159 },
- { 0x90074, 0xd49 },
- { 0x90075, 0x630 },
- { 0x90076, 0x159 },
- { 0x90077, 0x94a },
- { 0x90078, 0x630 },
- { 0x90079, 0x159 },
- { 0x9007a, 0x441 },
- { 0x9007b, 0x630 },
- { 0x9007c, 0x149 },
- { 0x9007d, 0x42 },
- { 0x9007e, 0x630 },
- { 0x9007f, 0x149 },
- { 0x90080, 0x1 },
- { 0x90081, 0x630 },
- { 0x90082, 0x149 },
- { 0x90083, 0x0 },
- { 0x90084, 0xe0 },
- { 0x90085, 0x109 },
- { 0x90086, 0xa },
- { 0x90087, 0x10 },
- { 0x90088, 0x109 },
- { 0x90089, 0x9 },
- { 0x9008a, 0x3c0 },
- { 0x9008b, 0x149 },
- { 0x9008c, 0x9 },
- { 0x9008d, 0x3c0 },
- { 0x9008e, 0x159 },
- { 0x9008f, 0x18 },
- { 0x90090, 0x10 },
- { 0x90091, 0x109 },
- { 0x90092, 0x0 },
- { 0x90093, 0x3c0 },
- { 0x90094, 0x109 },
- { 0x90095, 0x18 },
- { 0x90096, 0x4 },
- { 0x90097, 0x48 },
- { 0x90098, 0x18 },
- { 0x90099, 0x4 },
- { 0x9009a, 0x58 },
- { 0x9009b, 0xa },
- { 0x9009c, 0x10 },
- { 0x9009d, 0x109 },
- { 0x9009e, 0x2 },
- { 0x9009f, 0x10 },
- { 0x900a0, 0x109 },
- { 0x900a1, 0x5 },
- { 0x900a2, 0x7c0 },
- { 0x900a3, 0x109 },
- { 0x900a4, 0x10 },
- { 0x900a5, 0x10 },
- { 0x900a6, 0x109 },
- { 0x40000, 0x811 },
- { 0x40020, 0x880 },
- { 0x40040, 0x0 },
- { 0x40060, 0x0 },
- { 0x40001, 0x4008 },
- { 0x40021, 0x83 },
- { 0x40041, 0x4f },
- { 0x40061, 0x0 },
- { 0x40002, 0x4040 },
- { 0x40022, 0x83 },
- { 0x40042, 0x51 },
- { 0x40062, 0x0 },
- { 0x40003, 0x811 },
- { 0x40023, 0x880 },
- { 0x40043, 0x0 },
- { 0x40063, 0x0 },
- { 0x40004, 0x720 },
- { 0x40024, 0xf },
- { 0x40044, 0x1740 },
- { 0x40064, 0x0 },
- { 0x40005, 0x16 },
- { 0x40025, 0x83 },
- { 0x40045, 0x4b },
- { 0x40065, 0x0 },
- { 0x40006, 0x716 },
- { 0x40026, 0xf },
- { 0x40046, 0x2001 },
- { 0x40066, 0x0 },
- { 0x40007, 0x716 },
- { 0x40027, 0xf },
- { 0x40047, 0x2800 },
- { 0x40067, 0x0 },
- { 0x40008, 0x716 },
- { 0x40028, 0xf },
- { 0x40048, 0xf00 },
- { 0x40068, 0x0 },
- { 0x40009, 0x720 },
- { 0x40029, 0xf },
- { 0x40049, 0x1400 },
- { 0x40069, 0x0 },
- { 0x4000a, 0xe08 },
- { 0x4002a, 0xc15 },
- { 0x4004a, 0x0 },
- { 0x4006a, 0x0 },
- { 0x4000b, 0x623 },
- { 0x4002b, 0x15 },
- { 0x4004b, 0x0 },
- { 0x4006b, 0x0 },
- { 0x4000c, 0x4028 },
- { 0x4002c, 0x80 },
- { 0x4004c, 0x0 },
- { 0x4006c, 0x0 },
- { 0x4000d, 0xe08 },
- { 0x4002d, 0xc1a },
- { 0x4004d, 0x0 },
- { 0x4006d, 0x0 },
- { 0x4000e, 0x623 },
- { 0x4002e, 0x1a },
- { 0x4004e, 0x0 },
- { 0x4006e, 0x0 },
- { 0x4000f, 0x4040 },
- { 0x4002f, 0x80 },
- { 0x4004f, 0x0 },
- { 0x4006f, 0x0 },
- { 0x40010, 0x2604 },
- { 0x40030, 0x15 },
- { 0x40050, 0x0 },
- { 0x40070, 0x0 },
- { 0x40011, 0x708 },
- { 0x40031, 0x5 },
- { 0x40051, 0x0 },
- { 0x40071, 0x2002 },
- { 0x40012, 0x8 },
- { 0x40032, 0x80 },
- { 0x40052, 0x0 },
- { 0x40072, 0x0 },
- { 0x40013, 0x2604 },
- { 0x40033, 0x1a },
- { 0x40053, 0x0 },
- { 0x40073, 0x0 },
- { 0x40014, 0x708 },
- { 0x40034, 0xa },
- { 0x40054, 0x0 },
- { 0x40074, 0x2002 },
- { 0x40015, 0x4040 },
- { 0x40035, 0x80 },
- { 0x40055, 0x0 },
- { 0x40075, 0x0 },
- { 0x40016, 0x60a },
- { 0x40036, 0x15 },
- { 0x40056, 0x1200 },
- { 0x40076, 0x0 },
- { 0x40017, 0x61a },
- { 0x40037, 0x15 },
- { 0x40057, 0x1300 },
- { 0x40077, 0x0 },
- { 0x40018, 0x60a },
- { 0x40038, 0x1a },
- { 0x40058, 0x1200 },
- { 0x40078, 0x0 },
- { 0x40019, 0x642 },
- { 0x40039, 0x1a },
- { 0x40059, 0x1300 },
- { 0x40079, 0x0 },
- { 0x4001a, 0x4808 },
- { 0x4003a, 0x880 },
- { 0x4005a, 0x0 },
- { 0x4007a, 0x0 },
- { 0x900a7, 0x0 },
- { 0x900a8, 0x790 },
- { 0x900a9, 0x11a },
- { 0x900aa, 0x8 },
- { 0x900ab, 0x7aa },
- { 0x900ac, 0x2a },
- { 0x900ad, 0x10 },
- { 0x900ae, 0x7b2 },
- { 0x900af, 0x2a },
- { 0x900b0, 0x0 },
- { 0x900b1, 0x7c8 },
- { 0x900b2, 0x109 },
- { 0x900b3, 0x10 },
- { 0x900b4, 0x2a8 },
- { 0x900b5, 0x129 },
- { 0x900b6, 0x8 },
- { 0x900b7, 0x370 },
- { 0x900b8, 0x129 },
- { 0x900b9, 0xa },
- { 0x900ba, 0x3c8 },
- { 0x900bb, 0x1a9 },
- { 0x900bc, 0xc },
- { 0x900bd, 0x408 },
- { 0x900be, 0x199 },
- { 0x900bf, 0x14 },
- { 0x900c0, 0x790 },
- { 0x900c1, 0x11a },
- { 0x900c2, 0x8 },
- { 0x900c3, 0x4 },
- { 0x900c4, 0x18 },
- { 0x900c5, 0xe },
- { 0x900c6, 0x408 },
- { 0x900c7, 0x199 },
- { 0x900c8, 0x8 },
- { 0x900c9, 0x8568 },
- { 0x900ca, 0x108 },
- { 0x900cb, 0x18 },
- { 0x900cc, 0x790 },
- { 0x900cd, 0x16a },
- { 0x900ce, 0x8 },
- { 0x900cf, 0x1d8 },
- { 0x900d0, 0x169 },
- { 0x900d1, 0x10 },
- { 0x900d2, 0x8558 },
- { 0x900d3, 0x168 },
- { 0x900d4, 0x70 },
- { 0x900d5, 0x788 },
- { 0x900d6, 0x16a },
- { 0x900d7, 0x1ff8 },
- { 0x900d8, 0x85a8 },
- { 0x900d9, 0x1e8 },
- { 0x900da, 0x50 },
- { 0x900db, 0x798 },
- { 0x900dc, 0x16a },
- { 0x900dd, 0x60 },
- { 0x900de, 0x7a0 },
- { 0x900df, 0x16a },
- { 0x900e0, 0x8 },
- { 0x900e1, 0x8310 },
- { 0x900e2, 0x168 },
- { 0x900e3, 0x8 },
- { 0x900e4, 0xa310 },
- { 0x900e5, 0x168 },
- { 0x900e6, 0xa },
- { 0x900e7, 0x408 },
- { 0x900e8, 0x169 },
- { 0x900e9, 0x6e },
- { 0x900ea, 0x0 },
- { 0x900eb, 0x68 },
- { 0x900ec, 0x0 },
- { 0x900ed, 0x408 },
- { 0x900ee, 0x169 },
- { 0x900ef, 0x0 },
- { 0x900f0, 0x8310 },
- { 0x900f1, 0x168 },
- { 0x900f2, 0x0 },
- { 0x900f3, 0xa310 },
- { 0x900f4, 0x168 },
- { 0x900f5, 0x1ff8 },
- { 0x900f6, 0x85a8 },
- { 0x900f7, 0x1e8 },
- { 0x900f8, 0x68 },
- { 0x900f9, 0x798 },
- { 0x900fa, 0x16a },
- { 0x900fb, 0x78 },
- { 0x900fc, 0x7a0 },
- { 0x900fd, 0x16a },
- { 0x900fe, 0x68 },
- { 0x900ff, 0x790 },
- { 0x90100, 0x16a },
- { 0x90101, 0x8 },
- { 0x90102, 0x8b10 },
- { 0x90103, 0x168 },
- { 0x90104, 0x8 },
- { 0x90105, 0xab10 },
- { 0x90106, 0x168 },
- { 0x90107, 0xa },
- { 0x90108, 0x408 },
- { 0x90109, 0x169 },
- { 0x9010a, 0x58 },
- { 0x9010b, 0x0 },
- { 0x9010c, 0x68 },
- { 0x9010d, 0x0 },
- { 0x9010e, 0x408 },
- { 0x9010f, 0x169 },
- { 0x90110, 0x0 },
- { 0x90111, 0x8b10 },
- { 0x90112, 0x168 },
- { 0x90113, 0x0 },
- { 0x90114, 0xab10 },
- { 0x90115, 0x168 },
- { 0x90116, 0x0 },
- { 0x90117, 0x1d8 },
- { 0x90118, 0x169 },
- { 0x90119, 0x80 },
- { 0x9011a, 0x790 },
- { 0x9011b, 0x16a },
- { 0x9011c, 0x18 },
- { 0x9011d, 0x7aa },
- { 0x9011e, 0x6a },
- { 0x9011f, 0xa },
- { 0x90120, 0x0 },
- { 0x90121, 0x1e9 },
- { 0x90122, 0x8 },
- { 0x90123, 0x8080 },
- { 0x90124, 0x108 },
- { 0x90125, 0xf },
- { 0x90126, 0x408 },
- { 0x90127, 0x169 },
- { 0x90128, 0xc },
- { 0x90129, 0x0 },
- { 0x9012a, 0x68 },
- { 0x9012b, 0x9 },
- { 0x9012c, 0x0 },
- { 0x9012d, 0x1a9 },
- { 0x9012e, 0x0 },
- { 0x9012f, 0x408 },
- { 0x90130, 0x169 },
- { 0x90131, 0x0 },
- { 0x90132, 0x8080 },
- { 0x90133, 0x108 },
- { 0x90134, 0x8 },
- { 0x90135, 0x7aa },
- { 0x90136, 0x6a },
- { 0x90137, 0x0 },
- { 0x90138, 0x8568 },
- { 0x90139, 0x108 },
- { 0x9013a, 0xb7 },
- { 0x9013b, 0x790 },
- { 0x9013c, 0x16a },
- { 0x9013d, 0x1f },
- { 0x9013e, 0x0 },
- { 0x9013f, 0x68 },
- { 0x90140, 0x8 },
- { 0x90141, 0x8558 },
- { 0x90142, 0x168 },
- { 0x90143, 0xf },
- { 0x90144, 0x408 },
- { 0x90145, 0x169 },
- { 0x90146, 0xc },
- { 0x90147, 0x0 },
- { 0x90148, 0x68 },
- { 0x90149, 0x0 },
- { 0x9014a, 0x408 },
- { 0x9014b, 0x169 },
- { 0x9014c, 0x0 },
- { 0x9014d, 0x8558 },
- { 0x9014e, 0x168 },
- { 0x9014f, 0x8 },
- { 0x90150, 0x3c8 },
- { 0x90151, 0x1a9 },
- { 0x90152, 0x3 },
- { 0x90153, 0x370 },
- { 0x90154, 0x129 },
- { 0x90155, 0x20 },
- { 0x90156, 0x2aa },
- { 0x90157, 0x9 },
- { 0x90158, 0x0 },
- { 0x90159, 0x400 },
- { 0x9015a, 0x10e },
- { 0x9015b, 0x8 },
- { 0x9015c, 0xe8 },
- { 0x9015d, 0x109 },
- { 0x9015e, 0x0 },
- { 0x9015f, 0x8140 },
- { 0x90160, 0x10c },
- { 0x90161, 0x10 },
- { 0x90162, 0x8138 },
- { 0x90163, 0x10c },
- { 0x90164, 0x8 },
- { 0x90165, 0x7c8 },
- { 0x90166, 0x101 },
- { 0x90167, 0x8 },
- { 0x90168, 0x0 },
- { 0x90169, 0x8 },
- { 0x9016a, 0x8 },
- { 0x9016b, 0x448 },
- { 0x9016c, 0x109 },
- { 0x9016d, 0xf },
- { 0x9016e, 0x7c0 },
- { 0x9016f, 0x109 },
- { 0x90170, 0x0 },
- { 0x90171, 0xe8 },
- { 0x90172, 0x109 },
- { 0x90173, 0x47 },
- { 0x90174, 0x630 },
- { 0x90175, 0x109 },
- { 0x90176, 0x8 },
- { 0x90177, 0x618 },
- { 0x90178, 0x109 },
- { 0x90179, 0x8 },
- { 0x9017a, 0xe0 },
- { 0x9017b, 0x109 },
- { 0x9017c, 0x0 },
- { 0x9017d, 0x7c8 },
- { 0x9017e, 0x109 },
- { 0x9017f, 0x8 },
- { 0x90180, 0x8140 },
- { 0x90181, 0x10c },
- { 0x90182, 0x0 },
- { 0x90183, 0x1 },
- { 0x90184, 0x8 },
- { 0x90185, 0x8 },
- { 0x90186, 0x4 },
- { 0x90187, 0x8 },
- { 0x90188, 0x8 },
- { 0x90189, 0x7c8 },
- { 0x9018a, 0x101 },
- { 0x90006, 0x0 },
- { 0x90007, 0x0 },
- { 0x90008, 0x8 },
- { 0x90009, 0x0 },
- { 0x9000a, 0x0 },
- { 0x9000b, 0x0 },
- { 0xd00e7, 0x400 },
- { 0x90017, 0x0 },
- { 0x9001f, 0x2a },
- { 0x90026, 0x6a },
- { 0x400d0, 0x0 },
- { 0x400d1, 0x101 },
- { 0x400d2, 0x105 },
- { 0x400d3, 0x107 },
- { 0x400d4, 0x10f },
- { 0x400d5, 0x202 },
- { 0x400d6, 0x20a },
- { 0x400d7, 0x20b },
- { 0x2003a, 0x2 },
- { 0x2000b, 0x5d },
- { 0x2000c, 0xbb },
- { 0x2000d, 0x753 },
- { 0x2000e, 0x2c },
- { 0x12000b, 0xc },
- { 0x12000c, 0x19 },
- { 0x12000d, 0xfa },
- { 0x12000e, 0x10 },
- { 0x22000b, 0x3 },
- { 0x22000c, 0x6 },
- { 0x22000d, 0x3e },
- { 0x22000e, 0x10 },
- { 0x9000c, 0x0 },
- { 0x9000d, 0x173 },
- { 0x9000e, 0x60 },
- { 0x9000f, 0x6110 },
- { 0x90010, 0x2152 },
- { 0x90011, 0xdfbd },
- { 0x90012, 0x60 },
- { 0x90013, 0x6152 },
- { 0x20010, 0x5a },
- { 0x20011, 0x3 },
- { 0x40080, 0xe0 },
- { 0x40081, 0x12 },
- { 0x40082, 0xe0 },
- { 0x40083, 0x12 },
- { 0x40084, 0xe0 },
- { 0x40085, 0x12 },
- { 0x140080, 0xe0 },
- { 0x140081, 0x12 },
- { 0x140082, 0xe0 },
- { 0x140083, 0x12 },
- { 0x140084, 0xe0 },
- { 0x140085, 0x12 },
- { 0x240080, 0xe0 },
- { 0x240081, 0x12 },
- { 0x240082, 0xe0 },
- { 0x240083, 0x12 },
- { 0x240084, 0xe0 },
- { 0x240085, 0x12 },
- { 0x400fd, 0xf },
- { 0x10011, 0x1 },
- { 0x10012, 0x1 },
- { 0x10013, 0x180 },
- { 0x10018, 0x1 },
- { 0x10002, 0x6209 },
- { 0x100b2, 0x1 },
- { 0x101b4, 0x1 },
- { 0x102b4, 0x1 },
- { 0x103b4, 0x1 },
- { 0x104b4, 0x1 },
- { 0x105b4, 0x1 },
- { 0x106b4, 0x1 },
- { 0x107b4, 0x1 },
- { 0x108b4, 0x1 },
- { 0x11011, 0x1 },
- { 0x11012, 0x1 },
- { 0x11013, 0x180 },
- { 0x11018, 0x1 },
- { 0x11002, 0x6209 },
- { 0x110b2, 0x1 },
- { 0x111b4, 0x1 },
- { 0x112b4, 0x1 },
- { 0x113b4, 0x1 },
- { 0x114b4, 0x1 },
- { 0x115b4, 0x1 },
- { 0x116b4, 0x1 },
- { 0x117b4, 0x1 },
- { 0x118b4, 0x1 },
- { 0x12011, 0x1 },
- { 0x12012, 0x1 },
- { 0x12013, 0x180 },
- { 0x12018, 0x1 },
- { 0x12002, 0x6209 },
- { 0x120b2, 0x1 },
- { 0x121b4, 0x1 },
- { 0x122b4, 0x1 },
- { 0x123b4, 0x1 },
- { 0x124b4, 0x1 },
- { 0x125b4, 0x1 },
- { 0x126b4, 0x1 },
- { 0x127b4, 0x1 },
- { 0x128b4, 0x1 },
- { 0x13011, 0x1 },
- { 0x13012, 0x1 },
- { 0x13013, 0x180 },
- { 0x13018, 0x1 },
- { 0x13002, 0x6209 },
- { 0x130b2, 0x1 },
- { 0x131b4, 0x1 },
- { 0x132b4, 0x1 },
- { 0x133b4, 0x1 },
- { 0x134b4, 0x1 },
- { 0x135b4, 0x1 },
- { 0x136b4, 0x1 },
- { 0x137b4, 0x1 },
- { 0x138b4, 0x1 },
- { 0x2003a, 0x2 },
- { 0xc0080, 0x2 },
- { 0xd0000, 0x1 },
+};
The same as above.
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
- {
/* P0 3000mts 1D */.drate = 3000,.fw_type = FW_1D_IMAGE,.fsp_cfg = lpddr4_fsp0_cfg,.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),- },
- {
/* P0 3000mts 2D */.drate = 3000,.fw_type = FW_2D_IMAGE,.fsp_cfg = lpddr4_fsp0_2d_cfg,.fsp_cfg_num =ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
- },
- {
/* P1 400mts 1D */.drate = 400,.fw_type = FW_1D_IMAGE,.fsp_cfg = lpddr4_fsp1_cfg,.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),- },
- {
/* P1 100mts 1D */.drate = 100,.fw_type = FW_1D_IMAGE,.fsp_cfg = lpddr4_fsp2_cfg,.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),- },
+};
+/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = {
- .ddrc_cfg = lpddr4_ddrc_cfg,
- .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
- .ddrphy_cfg = lpddr4_ddrphy_cfg,
- .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
- .fsp_msg = lpddr4_dram_fsp_msg,
- .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
- .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
- .ddrphy_trained_csr_num =
ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
- .ddrphy_pie = lpddr4_phy_pie,
- .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
It would be best to get the above values calculated dynamically for this SoC.
+}; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c new file mode 100644 index 0000000000..cf1dfc2c2a --- /dev/null +++ b/board/freescale/imx8mm_evk/spl.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 NXP
- */
+#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch/imx8mm_pins.h> +#include <asm/arch/sys_proto.h> +#include <power/pmic.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <asm/arch/ddr.h>
+DECLARE_GLOBAL_DATA_PTR;
+void spl_dram_init(void) +{
- ddr_init(&dram_timing);
+}
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
PAD_CTL_PUE | \
PAD_CTL_PE | PAD_CTL_FSEL2)+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+static iomux_v3_cfg_t const usdhc3_pads[] = {
- IMX8MM_PAD_NAND_WE_B_USDHC3_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_WP_B_USDHC3_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
+static iomux_v3_cfg_t const usdhc2_pads[] = {
- IMX8MM_PAD_SD2_CLK_USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_SD2_CMD_USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 |
MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +};
+/*
- The evk board uses DAT3 to detect CD card plugin,
- in u-boot we mux the pin to GPIO when doing
board_mmc_getcd.
- */
+static iomux_v3_cfg_t const usdhc2_cd_pad =
- IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 |
MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); + +static iomux_v3_cfg_t const usdhc2_dat3_pad =
- IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
- MUX_PAD_CTRL(USDHC_PAD_CTRL);
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC2_BASE_ADDR, 0, 1},
- {USDHC3_BASE_ADDR, 0, 1},
+};
+int board_mmc_init(bd_t *bis) +{
- int i, ret;
- /*
* According to the board_mmc_init() the followingmap is done:
* (U-Boot device node) (Physical Port)* mmc0 USDHC1* mmc1 USDHC2*/- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {case 0:usdhc_cfg[0].sdhc_clk =mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO,"usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;case 1:usdhc_cfg[1].sdhc_clk =mxc_get_clock(MXC_ESDHC3_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads));
break;It would be best if you could enable DM/DTS in SPL too from the outset (and share the SPL size).
Do you have any timeline for converting SPL to DM/DTS?
default:printf("USDHC controllers %d notsupported \n", i + 1);
return -EINVAL;}ret = fsl_esdhc_initialize(bis,&usdhc_cfg[i]);
if (ret)return ret;- }
- return 0;
+}
+int board_mmc_getcd(struct mmc *mmc) +{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg
*)mmc->priv;
- int ret = 0;
- switch (cfg->esdhc_base) {
- case USDHC3_BASE_ADDR:
ret = 1;break;- case USDHC2_BASE_ADDR:
imx_iomux_v3_setup_pad(usdhc2_cd_pad);gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");gpio_direction_input(USDHC2_CD_GPIO);/** Since it is the DAT3 pin, this pin ispulled to
* low voltage if no card*/ret = gpio_get_value(USDHC2_CD_GPIO);imx_iomux_v3_setup_pad(usdhc2_dat3_pad);return ret;- }
- return 1;
+}
+void spl_board_init(void) +{
- puts("Normal Boot\n");
+}
+#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{
- /* Just empty function now - can't decide what to
choose */
- debug("%s: %s\n", __func__, name);
- return 0;
+} +#endif
+void board_init_f(ulong dummy) +{
- int ret;
- /* Clear global data */
- memset((void *)gd, 0, sizeof(gd_t));
- arch_cpu_init();
- init_uart_clk(1);
- board_early_init_f();
- timer_init();
- preloader_console_init();
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
- ret = spl_init();
- if (ret) {
debug("spl_init() failed: %d\n", ret);hang();- }
- enable_tzc380();
- /* DDR initialization */
- spl_dram_init();
- board_init_r(NULL, 0);
+} diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig new file mode 100644 index 0000000000..6110f23e38 --- /dev/null +++ b/configs/imx8mm_evk_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
/imximage.cfg,SPL_TEXT_BASE=0x7E1000"
+CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_DM_ETH=y
Here you enable the DM_ETH, but the welcome u-boot info says:
"Net: No ethernet found."
+CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h new file mode 100644 index 0000000000..f944308757 --- /dev/null +++ b/include/configs/imx8mm_evk.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2018 NXP
- */
+#ifndef __IMX8MM_EVK_H +#define __IMX8MM_EVK_H
+#include <linux/sizes.h> +#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif
+#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \
- (QSPI0_AMBA_BASE +
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
+#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x91fff0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define
CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR 0x00910000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image
gives a
error
info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100
Why do you need to undef those config options?
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#endif
+#define CONFIG_REMAKE_ELF
+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT
+/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP
+#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD
There seems to be some issue with inheritance, as you need to undef those values manually.
Why is it needed?
+/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC
+#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000
+#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif
+/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=Image\0" \
- "console=ttymxc1,115200
earlycon=ec_imx6q,0x30890000,115200\0" \
- "fdt_addr=0x43000000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "boot_fdt=try\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "initrd_addr=0x43800000\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
"\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs ${jh_clk} console=${console}
root=${mmcroot}\0 " \
- "loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
"source\0" \- "loadimage=fatload mmc ${mmcdev}:${mmcpart}
${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"if test ${boot_fdt} = yes || test${boot_fdt} = try; then " \
"if run loadfdt; then " \"booti ${loadaddr} -${fdt_addr}; " \
"else " \"echo WARN: Cannot load theDT; " \
"fi; " \"else " \"echo wait for boot; " \"fi;\0" \- "netargs=setenv bootargs ${jh_clk}
console=${console} " \
"root=/dev/nfs " \"ip=dhcpnfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${loadaddr} ${image}; " \"if test ${boot_fdt} = yes || test${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr}${fdt_file}; then " \
"booti ${loadaddr} -${fdt_addr}; " \
"else " \"echo WARN: Cannot load theDT; " \
"fi; " \"else " \"booti; " \"fi;\0"+#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \"else booti ${loadaddr} - ${fdt_addr}; fi"+/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#endif +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END
(CONFIG_SYS_MEMTEST_START +
(PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE
- \ +
sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX
+/* USDHC */ +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000
Some of those values are (SYS_I2C_*, MXC_OCOTP, FSL_*) are already supported by Kconfig. Please use Kconfig instead.
+#define CONFIG_OF_SYSTEM_SETUP
+#endif
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de