10 Jan
2017
10 Jan
'17
10:27 a.m.
09.01.2017, 18:01, "Maxime Ripard" maxime.ripard@free-electrons.com:
On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote:
> > + MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ | > > What's wrong about it?
V3s DRAM seems to be 16-bit.
However, boot0 has this bit set, and without this bit, it cannot work.
According to Jens' guess (only guess), this may be something more like full-width and half-width.
Ok. Please put that in the comments then.
Now I think it's not only guess.
See dram_sun8i_a33.h, which has MCTL_CR_BUSW8 = 0 << 12 and MCTL_CR_BUSW16 = 1 << 12.
Thanks! Maxime
-- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com