Re: [U-Boot] [PATCH] sh: add support for sh7757lcr board

On Mon, Jan 17, 2011 at 01:11:08PM +0900, Yoshihiro Shimoda wrote:

The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM, Ethernet, and more.

This patch supports the following functions:

• 256MB DDR3-SDRAM
• SPI ROM
• Ethernet

Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com

arch/sh/include/asm/cpu_sh4.h | 2 + arch/sh/include/asm/cpu_sh7757.h | 263 +++++++++++++++ board/renesas/sh7757lcr/Makefile | 42 +++ board/renesas/sh7757lcr/config.mk | 28 ++ board/renesas/sh7757lcr/lowlevel_init.S | 558 +++++++++++++++++++++++++++++++ board/renesas/sh7757lcr/sh7757lcr.c | 436 ++++++++++++++++++++++++ board/renesas/sh7757lcr/spi-boot.c | 111 ++++++ board/renesas/sh7757lcr/u-boot.lds | 101 ++++++ boards.cfg | 1 + doc/README.sh7757lcr | 64 ++++ include/configs/sh7757lcr.h | 143 ++++++++ 11 files changed, 1749 insertions(+), 0 deletions(-) create mode 100644 arch/sh/include/asm/cpu_sh7757.h create mode 100644 board/renesas/sh7757lcr/Makefile create mode 100644 board/renesas/sh7757lcr/config.mk create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c create mode 100644 board/renesas/sh7757lcr/spi-boot.c create mode 100644 board/renesas/sh7757lcr/u-boot.lds create mode 100644 doc/README.sh7757lcr create mode 100644 include/configs/sh7757lcr.h

diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index fdcebd6..9b29d3a 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -44,6 +44,8 @@ # include <asm/cpu_sh7722.h> #elif defined (CONFIG_CPU_SH7723) # include <asm/cpu_sh7723.h> +#elif defined (CONFIG_CPU_SH7757) +# include <asm/cpu_sh7757.h> #elif defined (CONFIG_CPU_SH7763) # include <asm/cpu_sh7763.h> #elif defined (CONFIG_CPU_SH7780) diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h new file mode 100644 index 0000000..eb9ff5b --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7757.h @@ -0,0 +1,263 @@ +/*

• • Copyright (C) 2011 Renesas Solutions Corp.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef _ASM_CPU_SH7757_H_ +#define _ASM_CPU_SH7757_H_

+#define CCR 0xFF00001C +#define WTCNT 0xFFCC0000 +#define CCR_CACHE_INIT 0x0000090b +#define CACHE_OC_NUM_WAYS 1

+/* Exception */ +#define EXPEVT 0xff000024 +#define INTEVT 0xff000028

+/* Watchdog */ +#define WTCSR0 0xffcc0002 +#define WRSTCSR_R 0xffcc0003 +#define WRSTCSR_W 0xffcc0002 +#define WTCSR_PREFIX 0xa500 +#define WRSTCSR_PREFIX 0x6900 +#define WRSTCSR_WOVF_PREFIX 0x9600

+/* SCIF */ +#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ +#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ +#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */

+/* SerMux */ +#define SMR0 0xfe470000

+/* TMU0 */ +#define TSTR 0xFE430004 +#define TOCR 0xFE430000 +#define TSTR0 0xFE430004 +#define TCOR0 0xFE430008 +#define TCNT0 0xFE43000C +#define TCR0 0xFE430010 +#define TCOR1 0xFE430014 +#define TCNT1 0xFE430018 +#define TCR1 0xFE43001C +#define TCOR2 0xFE430020 +#define TCNT2 0xFE430024 +#define TCR2 0xFE430028 +#define TCPR2 0xFE43002C

+/* BSC */ +#define BCR 0xFE801000 +#define CS0BCR 0xFF802000 +#define CS0WCR 0xFF802008 +#define CS4BCR 0xFF802040 +#define CS4WCR 0xFF802048 +#define CS5BCR 0xFF802050 +#define CS5WCR 0xFF802058 +#define CS6BCR 0xFF802060 +#define CS6WCR 0xFF802068

+/* DDR3IF */ +#define DDR3IF_BASE 0xfe800000 +#define DBSTATE0 (DDR3IF_BASE + 0x0008) +#define DBSTATE1 (DDR3IF_BASE + 0x000c) +#define DBACEN (DDR3IF_BASE + 0x0010) +#define DBRFEN (DDR3IF_BASE + 0x0014) +#define DBCMD (DDR3IF_BASE + 0x0018) +#define DBWAIT (DDR3IF_BASE + 0x001c) +#define DBKIND (DDR3IF_BASE + 0x0020) +#define DBCONF (DDR3IF_BASE + 0x0024) +#define DBTR0 (DDR3IF_BASE + 0x0040) +#define DBTR1 (DDR3IF_BASE + 0x0044) +#define DBTR2 (DDR3IF_BASE + 0x0048) +#define DBTR3 (DDR3IF_BASE + 0x0050) +#define DBTR4 (DDR3IF_BASE + 0x0054) +#define DBTR5 (DDR3IF_BASE + 0x0058) +#define DBTR6 (DDR3IF_BASE + 0x005c) +#define DBTR7 (DDR3IF_BASE + 0x0060) +#define DBTR8 (DDR3IF_BASE + 0x0064) +#define DBTR9 (DDR3IF_BASE + 0x0068) +#define DBTR10 (DDR3IF_BASE + 0x006c) +#define DBTR11 (DDR3IF_BASE + 0x0070) +#define DBTR12 (DDR3IF_BASE + 0x0074) +#define DBTR13 (DDR3IF_BASE + 0x0078) +#define DBTR14 (DDR3IF_BASE + 0x007c) +#define DBTR15 (DDR3IF_BASE + 0x0080) +#define DBTR16 (DDR3IF_BASE + 0x0084) +#define DBTR17 (DDR3IF_BASE + 0x0088) +#define DBTR18 (DDR3IF_BASE + 0x008c) +#define DBTR19 (DDR3IF_BASE + 0x0090) +#define DBADJ0 (DDR3IF_BASE + 0x00c0) +#define DBADJ1 (DDR3IF_BASE + 0x00c4) +#define DBADJ2 (DDR3IF_BASE + 0x00c8) +#define DBADJ3 (DDR3IF_BASE + 0x00cc) +#define DBRFCNF0 (DDR3IF_BASE + 0x00e0) +#define DBRFCNF1 (DDR3IF_BASE + 0x00e4) +#define DBRFCNF2 (DDR3IF_BASE + 0x00e8) +#define DBCALCNF (DDR3IF_BASE + 0x00f4) +#define DBRNK0 (DDR3IF_BASE + 0x0100) +#define DBPDCNT0 (DDR3IF_BASE + 0x0200) +#define DBPDCNT1 (DDR3IF_BASE + 0x0204) +#define DBPDCNT2 (DDR3IF_BASE + 0x0208) +#define DBPDCNT3 (DDR3IF_BASE + 0x020c) +#define DBPDLCK (DDR3IF_BASE + 0x0280) +#define DBPDRGA (DDR3IF_BASE + 0x0290) +#define DBPDRGD (DDR3IF_BASE + 0x02a0) +#define DBBS0CNT0 (DDR3IF_BASE + 0x0300) +#define DBBS0CNT1 (DDR3IF_BASE + 0x0304)

+/* DDR-ECC */ +#define ECD_ECDEN 0xffc1012c +#define ECD_MCR 0xfe900010 +#define ECD_SPACER 0xfe900018 +#define ECD_INTSR 0xfe900024

+/* GPIO */ +#define GPIO_BASE 0xffec0000 +#define PACR (GPIO_BASE + 0x0000) +#define PBCR (GPIO_BASE + 0x0002) +#define PCCR (GPIO_BASE + 0x0004) +#define PDCR (GPIO_BASE + 0x0006) +#define PECR (GPIO_BASE + 0x0008) +#define PFCR (GPIO_BASE + 0x000a) +#define PGCR (GPIO_BASE + 0x000c) +#define PHCR (GPIO_BASE + 0x000e) +#define PICR (GPIO_BASE + 0x0010) +#define PJCR (GPIO_BASE + 0x0012) +#define PKCR (GPIO_BASE + 0x0014) +#define PLCR (GPIO_BASE + 0x0016) +#define PMCR (GPIO_BASE + 0x0018) +#define PNCR (GPIO_BASE + 0x001a) +#define POCR (GPIO_BASE + 0x001c) +#define PPCR (GPIO_BASE + 0x001e) +#define PQCR (GPIO_BASE + 0x0020) +#define PRCR (GPIO_BASE + 0x0022) +#define PSCR (GPIO_BASE + 0x0024) +#define PTCR (GPIO_BASE + 0x0026) +#define PUCR (GPIO_BASE + 0x0028) +#define PVCR (GPIO_BASE + 0x002a) +#define PWCR (GPIO_BASE + 0x002c) +#define PXCR (GPIO_BASE + 0x002e) +#define PYCR (GPIO_BASE + 0x0030) +#define PZCR (GPIO_BASE + 0x0032) +#define PADR (GPIO_BASE + 0x0034) +#define PBDR (GPIO_BASE + 0x0036) +#define PCDR (GPIO_BASE + 0x0038) +#define PDDR (GPIO_BASE + 0x003a) +#define PEDR (GPIO_BASE + 0x003c) +#define PFDR (GPIO_BASE + 0x003e) +#define PGDR (GPIO_BASE + 0x0040) +#define PHDR (GPIO_BASE + 0x0042) +#define PIDR (GPIO_BASE + 0x0044) +#define PJDR (GPIO_BASE + 0x0046) +#define PKDR (GPIO_BASE + 0x0048) +#define PLDR (GPIO_BASE + 0x004a) +#define PMDR (GPIO_BASE + 0x004c) +#define PNDR (GPIO_BASE + 0x004e) +#define PODR (GPIO_BASE + 0x0050) +#define PPDR (GPIO_BASE + 0x0052) +#define PQDR (GPIO_BASE + 0x0054) +#define PRDR (GPIO_BASE + 0x0056) +#define PSDR (GPIO_BASE + 0x0058) +#define PTDR (GPIO_BASE + 0x005a) +#define PUDR (GPIO_BASE + 0x005c) +#define PVDR (GPIO_BASE + 0x005e) +#define PWDR (GPIO_BASE + 0x0060) +#define PXDR (GPIO_BASE + 0x0062) +#define PYDR (GPIO_BASE + 0x0064) +#define PZDR (GPIO_BASE + 0x0066) +#define PSEL0 (GPIO_BASE + 0x0070) +#define PSEL1 (GPIO_BASE + 0x0072) +#define PSEL2 (GPIO_BASE + 0x0074) +#define PSEL3 (GPIO_BASE + 0x0076) +#define PSEL4 (GPIO_BASE + 0x0078) +#define PSEL5 (GPIO_BASE + 0x007a) +#define PSEL6 (GPIO_BASE + 0x007c) +#define PSEL7 (GPIO_BASE + 0x0082) +#define PSEL8 (GPIO_BASE + 0x0084)

+/* GETHER */ +#define GETHER_GBECONT 0xffc10100 +#define GBECONT_RMII1 0x00020000 +#define GBECONT_RMII0 0x00010000

+/* USB1 */ +#define USB1_PORT1SEL 0xfe4f2000 +#define USB1_EHCIDATAC 0xfe4fe018 +#define USB1_OHCIDATAC 0xfe4fe118 +#define USB0_PHY_RESET 0xfe5f0000 +#define USB0_PHY_PORTSEL 0xfe5f000a +#define USB0_SUSPMODE 0xfe450102 +#define USB1_SUSPMODE 0xfe4f0102

+/* GCTRL */ +#define GCTRL_BASE 0xffc10000 +#define GCTRL_WPROTECT (GCTRL_BASE + 0x0000) +#define GCTRL_GPLLDIV (GCTRL_BASE + 0x0004) +#define GCTRL_GRACR3 (GCTRL_BASE + 0x000c) +#define GCTRL_FCNTCR1 (GCTRL_BASE + 0x0020) +#define GCTRL_FCNTCR2 (GCTRL_BASE + 0x0024) +#define GCTRL_MSTPCR2 (GCTRL_BASE + 0x0028) +#define GCTRL_GPLL1DIV (GCTRL_BASE + 0x0030) +#define GCTRL_VCOMPSEL (GCTRL_BASE + 0x0034) +#define GCTRL_SPIBOOTCAN (GCTRL_BASE + 0x1000)

+/* PCIe */ +#define PCIE_BASE 0xffca0000 +#define PCIE_PCICONF14 (PCIE_BASE + 0x003c) +#define PCIE_MSICAP0 (PCIE_BASE + 0x0050) +#define PCIE_LAD0 (PCIE_BASE + 0x1260) +#define PCIE_LADMSK0 (PCIE_BASE + 0x1264) +#define PCIE_LAD1 (PCIE_BASE + 0x1268) +#define PCIE_LADMSK1 (PCIE_BASE + 0x126c) +#define PCIE_LAD2 (PCIE_BASE + 0x1270) +#define PCIE_LADMSK2 (PCIE_BASE + 0x1274) +#define PCIE_LAD3 (PCIE_BASE + 0x1278) +#define PCIE_LADMSK3 (PCIE_BASE + 0x127c) +#define PCIE_LAD4 (PCIE_BASE + 0x1280) +#define PCIE_LADMSK4 (PCIE_BASE + 0x1284) +#define PCIE_LAD5 (PCIE_BASE + 0x1288) +#define PCIE_LADMSK5 (PCIE_BASE + 0x128c) +#define PCIE_BARMAP0 (PCIE_BASE + 0x1420) +#define PCIE_PBICTL3 (PCIE_BASE + 0x142C) +#define PCIE_PBICTL2 (PCIE_BASE + 0x1470) +#define PCIE_BSTCTL0 (PCIE_BASE + 0x1604) +#define PCIE_ENDICTL0 (PCIE_BASE + 0x160c) +#define PCIE_ENDICTL1 (PCIE_BASE + 0x1610)

+/* PCIe-Bridge */ +#define PCIEBRG_BASE 0xffd60000 +#define PCIEBRG_CTRL_H8S (PCIEBRG_BASE + 0x00) +#define PCIEBRG_CP_ADDR (PCIEBRG_BASE + 0x10) +#define PCIEBRG_CP_DATA (PCIEBRG_BASE + 0x14) +#define PCIEBRG_CP_CTRL (PCIEBRG_BASE + 0x18)

+/* CPU version */ +#define CCN_PRR 0xff000044 +#define prr_mask(_val) ((_val >> 4) & 0xff) +#define PRR_SH7757_B0 0x10 +#define PRR_SH7757_C0 0x11

+#define is_sh7757_b0(_val) \ +({ \

• int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
• __ret; \

+})

+#endif /* _ASM_CPU_SH7757_H_ */ diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile new file mode 100644 index 0000000..22106fd --- /dev/null +++ b/board/renesas/sh7757lcr/Makefile @@ -0,0 +1,42 @@ +# +# Copyright (C) 2011 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(BOARD).o

+COBJS := sh7757lcr.o spi-boot.o +SOBJS := lowlevel_init.o

+$(LIB): $(obj).depend $(COBJS) $(SOBJS)

• $(call cmd_link_o_target, $(COBJS) $(SOBJS))

+clean:

• rm -f $(SOBJS) $(OBJS)

+distclean: clean

• rm -f $(LIB) core *.bak $(obj).depend

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+######################################################################### diff --git a/board/renesas/sh7757lcr/config.mk b/board/renesas/sh7757lcr/config.mk new file mode 100644 index 0000000..514f52a --- /dev/null +++ b/board/renesas/sh7757lcr/config.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu iwamatsu@nigauri.org +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA

+# +# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +LDSCRIPT = $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds +#sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp

Is this nesseary?

+CONFIG_SYS_TEXT_BASE = 0x8ef80000

Please move this to config file of board.

diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S new file mode 100644 index 0000000..db4bf70 --- /dev/null +++ b/board/renesas/sh7757lcr/lowlevel_init.S @@ -0,0 +1,558 @@ +/*

• • Copyright (C) 2011 Renesas Solutions Corp.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h>

+.macro or32, addr, data

• mov.l \addr, r1
• mov.l \data, r0
• mov.l @r1, r2
• or r2, r0
• mov.l r0, @r1

+.endm

+.macro wait_DBCMD

• mov.l DBWAIT_A, r0
• mov.l @r0, r1

+.endm

• .global lowlevel_init
• .section .spiboot1.text
• .align 2

+lowlevel_init:

• /*------- GPIO -------*/
• write8 PGDR_A, PGDR_D /* eMMC power off */
• write16 PACR_A, PACR_D
• write16 PBCR_A, PBCR_D
• write16 PCCR_A, PCCR_D
• write16 PDCR_A, PDCR_D
• write16 PECR_A, PECR_D
• write16 PFCR_A, PFCR_D
• write16 PGCR_A, PGCR_D
• write16 PHCR_A, PHCR_D
• write16 PICR_A, PICR_D
• write16 PJCR_A, PJCR_D
• write16 PKCR_A, PKCR_D
• write16 PLCR_A, PLCR_D
• write16 PMCR_A, PMCR_D
• write16 PNCR_A, PNCR_D
• write16 POCR_A, POCR_D
• write16 PQCR_A, PQCR_D
• write16 PRCR_A, PRCR_D
• write16 PSCR_A, PSCR_D
• write16 PTCR_A, PTCR_D
• write16 PUCR_A, PUCR_D
• write16 PVCR_A, PVCR_D
• write16 PWCR_A, PWCR_D
• write16 PXCR_A, PXCR_D
• write16 PYCR_A, PYCR_D
• write16 PZCR_A, PZCR_D
• write16 PSEL0_A, PSEL0_D
• write16 PSEL1_A, PSEL1_D
• write16 PSEL2_A, PSEL2_D
• write16 PSEL3_A, PSEL3_D
• write16 PSEL4_A, PSEL4_D
• write16 PSEL5_A, PSEL5_D
• write16 PSEL6_A, PSEL6_D
• write16 PSEL7_A, PSEL7_D
• write16 PSEL8_A, PSEL8_D
• bra exit_gpio
• nop
• .align 4

+/*------- GPIO -------*/ +PGDR_A: .long PGDR +PACR_A: .long PACR +PBCR_A: .long PBCR +PCCR_A: .long PCCR +PDCR_A: .long PDCR +PECR_A: .long PECR +PFCR_A: .long PFCR +PGCR_A: .long PGCR +PHCR_A: .long PHCR +PICR_A: .long PICR +PJCR_A: .long PJCR +PKCR_A: .long PKCR +PLCR_A: .long PLCR +PMCR_A: .long PMCR +PNCR_A: .long PNCR +POCR_A: .long POCR +PQCR_A: .long PQCR +PRCR_A: .long PRCR +PSCR_A: .long PSCR +PTCR_A: .long PTCR +PUCR_A: .long PUCR +PVCR_A: .long PVCR +PWCR_A: .long PWCR +PXCR_A: .long PXCR +PYCR_A: .long PYCR +PZCR_A: .long PZCR +PSEL0_A: .long PSEL0 +PSEL1_A: .long PSEL1 +PSEL2_A: .long PSEL2 +PSEL3_A: .long PSEL3 +PSEL4_A: .long PSEL4 +PSEL5_A: .long PSEL5 +PSEL6_A: .long PSEL6 +PSEL7_A: .long PSEL7 +PSEL8_A: .long PSEL8

+PGDR_D: .long 0x80 +PACR_D: .long 0x0000 +PBCR_D: .long 0x0001 +PCCR_D: .long 0x0000 +PDCR_D: .long 0x0000 +PECR_D: .long 0x0000 +PFCR_D: .long 0x0000 +PGCR_D: .long 0x0000 +PHCR_D: .long 0x0000 +PICR_D: .long 0x0000 +PJCR_D: .long 0x0000 +PKCR_D: .long 0x0003 +PLCR_D: .long 0x0000 +PMCR_D: .long 0x0000 +PNCR_D: .long 0x0000 +POCR_D: .long 0x0000 +PQCR_D: .long 0xc000 +PRCR_D: .long 0x0000 +PSCR_D: .long 0x0000 +PTCR_D: .long 0x0000 +#if defined(CONFIG_SH7757_OFFSET_SPI) +PUCR_D: .long 0x0055 +#else +PUCR_D: .long 0x0000 +#endif +PVCR_D: .long 0x0000 +PWCR_D: .long 0x0000 +PXCR_D: .long 0x0000 +PYCR_D: .long 0x0000 +PZCR_D: .long 0x0000 +PSEL0_D: .long 0xfe00 +PSEL1_D: .long 0x0000 +PSEL2_D: .long 0x3000 +PSEL3_D: .long 0xff00 +PSEL4_D: .long 0x771f +PSEL5_D: .long 0x0ffc +PSEL6_D: .long 0x00ff +PSEL7_D: .long 0xfc00 +PSEL8_D: .long 0x0000

• .align 2

+exit_gpio:

• mov #0, r14
• mova 2f, r0
• mov.l PC_MASK, r1
• tst r0, r1
• bf 2f
• bra exit_pmb
• nop
• .align 2

+/* If CPU runs on SDRAM, PC is 0x8???????. */ +PC_MASK: .long 0x20000000

+2:

• mov #1, r14
• mov.l EXPEVT_A, r0
• mov.l @r0, r0
• mov.l EXPEVT_POWER_ON_RESET, r1
• cmp/eq r0, r1
• bt 1f
• /*

• * If EXPEVT value is manual reset or tlb multipul-hit,
  

• * initialization of DDR3IF is not necessary.
  

• */
  

• bra exit_ddr
• nop

+1:

• /* For Core Reset */
• mov.l DBACEN_A, r0
• mov.l @r0, r0
• cmp/eq #0, r0
• bt 3f
• /*

• * If DBACEN == 1(DBSC was already enabled), we have to avoid the
  

• * initialization of DDR3-SDRAM.
  

• */
  

• bra exit_ddr
• nop

+3:

• /*------- DDR3IF -------*/
• /* oscillation stabilization time */
• wait_timer WAIT_OSC_TIME
• /* step 3 */
• write32 DBCMD_A, DBCMD_RSTL_VAL
• wait_timer WAIT_30US
• /* step 4 */
• write32 DBCMD_A, DBCMD_PDEN_VAL
• /* step 5 */
• write32 DBKIND_A, DBKIND_D
• /* step 6 */
• write32 DBCONF_A, DBCONF_D
• write32 DBTR0_A, DBTR0_D
• write32 DBTR1_A, DBTR1_D
• write32 DBTR2_A, DBTR2_D
• write32 DBTR3_A, DBTR3_D
• write32 DBTR4_A, DBTR4_D
• write32 DBTR5_A, DBTR5_D
• write32 DBTR6_A, DBTR6_D
• write32 DBTR7_A, DBTR7_D
• write32 DBTR8_A, DBTR8_D
• write32 DBTR9_A, DBTR9_D
• write32 DBTR10_A, DBTR10_D
• write32 DBTR11_A, DBTR11_D
• write32 DBTR12_A, DBTR12_D
• write32 DBTR13_A, DBTR13_D
• write32 DBTR14_A, DBTR14_D
• write32 DBTR15_A, DBTR15_D
• write32 DBTR16_A, DBTR16_D
• write32 DBTR17_A, DBTR17_D
• write32 DBTR18_A, DBTR18_D
• write32 DBTR19_A, DBTR19_D
• write32 DBRNK0_A, DBRNK0_D
• /* step 7 */
• write32 DBPDCNT3_A, DBPDCNT3_D
• /* step 8 */
• write32 DBPDCNT1_A, DBPDCNT1_D
• write32 DBPDCNT2_A, DBPDCNT2_D
• write32 DBPDLCK_A, DBPDLCK_D
• write32 DBPDRGA_A, DBPDRGA_D
• write32 DBPDRGD_A, DBPDRGD_D
• /* step 9 */
• wait_timer WAIT_30US
• /* step 10 */
• write32 DBPDCNT0_A, DBPDCNT0_D
• /* step 11 */
• wait_timer WAIT_30US
• wait_timer WAIT_30US
• /* step 12 */
• write32 DBCMD_A, DBCMD_WAIT_VAL
• wait_DBCMD
• /* step 13 */
• write32 DBCMD_A, DBCMD_RSTH_VAL
• wait_DBCMD
• /* step 14 */
• write32 DBCMD_A, DBCMD_WAIT_VAL
• write32 DBCMD_A, DBCMD_WAIT_VAL
• write32 DBCMD_A, DBCMD_WAIT_VAL
• write32 DBCMD_A, DBCMD_WAIT_VAL
• /* step 15 */
• write32 DBCMD_A, DBCMD_PDXT_VAL
• /* step 16 */
• write32 DBCMD_A, DBCMD_MRS2_VAL
• /* step 17 */
• write32 DBCMD_A, DBCMD_MRS3_VAL
• /* step 18 */
• write32 DBCMD_A, DBCMD_MRS1_VAL
• /* step 19 */
• write32 DBCMD_A, DBCMD_MRS0_VAL
• /* step 20 */
• write32 DBCMD_A, DBCMD_ZQCL_VAL
• write32 DBCMD_A, DBCMD_REF_VAL
• write32 DBCMD_A, DBCMD_REF_VAL
• wait_DBCMD
• /* step 21 */
• write32 DBADJ0_A, DBADJ0_D
• write32 DBADJ1_A, DBADJ1_D
• write32 DBADJ2_A, DBADJ2_D
• /* step 22 */
• write32 DBRFCNF0_A, DBRFCNF0_D
• write32 DBRFCNF1_A, DBRFCNF1_D
• write32 DBRFCNF2_A, DBRFCNF2_D
• /* step 23 */
• write32 DBCALCNF_A, DBCALCNF_D
• /* step 24 */
• write32 DBRFEN_A, DBRFEN_D
• write32 DBCMD_A, DBCMD_SRXT_VAL
• /* step 25 */
• write32 DBACEN_A, DBACEN_D
• /* step 26 */
• wait_DBCMD
• /* enable DDR-ECC */
• write32 ECD_ECDEN_A, ECD_ECDEN_D
• write32 ECD_INTSR_A, ECD_INTSR_D
• write32 ECD_SPACER_A, ECD_SPACER_D
• write32 ECD_MCR_A, ECD_MCR_D
• bra exit_ddr
• nop
• .align 4

+EXPEVT_A: .long EXPEVT +EXPEVT_POWER_ON_RESET: .long 0x00000000

+/*------- DDR3IF -------*/ +DBCMD_A: .long DBCMD +DBKIND_A: .long DBKIND +DBCONF_A: .long DBCONF +DBTR0_A: .long DBTR0 +DBTR1_A: .long DBTR1 +DBTR2_A: .long DBTR2 +DBTR3_A: .long DBTR3 +DBTR4_A: .long DBTR4 +DBTR5_A: .long DBTR5 +DBTR6_A: .long DBTR6 +DBTR7_A: .long DBTR7 +DBTR8_A: .long DBTR8 +DBTR9_A: .long DBTR9 +DBTR10_A: .long DBTR10 +DBTR11_A: .long DBTR11 +DBTR12_A: .long DBTR12 +DBTR13_A: .long DBTR13 +DBTR14_A: .long DBTR14 +DBTR15_A: .long DBTR15 +DBTR16_A: .long DBTR16 +DBTR17_A: .long DBTR17 +DBTR18_A: .long DBTR18 +DBTR19_A: .long DBTR19 +DBRNK0_A: .long DBRNK0 +DBPDCNT0_A: .long DBPDCNT0 +DBPDCNT1_A: .long DBPDCNT1 +DBPDCNT2_A: .long DBPDCNT2 +DBPDCNT3_A: .long DBPDCNT3 +DBPDLCK_A: .long DBPDLCK +DBPDRGA_A: .long DBPDRGA +DBPDRGD_A: .long DBPDRGD +DBADJ0_A: .long DBADJ0 +DBADJ1_A: .long DBADJ1 +DBADJ2_A: .long DBADJ2 +DBRFCNF0_A: .long DBRFCNF0 +DBRFCNF1_A: .long DBRFCNF1 +DBRFCNF2_A: .long DBRFCNF2 +DBCALCNF_A: .long DBCALCNF +DBRFEN_A: .long DBRFEN +DBACEN_A: .long DBACEN +DBWAIT_A: .long DBWAIT

+WAIT_OSC_TIME: .long 6000 +WAIT_30US: .long 13333

+DBCMD_RSTL_VAL: .long 0x20000000 +DBCMD_PDEN_VAL: .long 0x1000d73c +DBCMD_WAIT_VAL: .long 0x0000d73c +DBCMD_RSTH_VAL: .long 0x2100d73c +DBCMD_PDXT_VAL: .long 0x110000c8 +DBCMD_MRS0_VAL: .long 0x28000930 +DBCMD_MRS1_VAL: .long 0x29000004 +DBCMD_MRS2_VAL: .long 0x2a000008 +DBCMD_MRS3_VAL: .long 0x2b000000 +DBCMD_ZQCL_VAL: .long 0x03000200 +DBCMD_REF_VAL: .long 0x0c000000 +DBCMD_SRXT_VAL: .long 0x19000000 +DBKIND_D: .long 0x00000007 +DBCONF_D: .long 0x0f030a01 +DBTR0_D: .long 0x00000007 +DBTR1_D: .long 0x00000006 +DBTR2_D: .long 0x00000000 +DBTR3_D: .long 0x00000007 +DBTR4_D: .long 0x00070007 +DBTR5_D: .long 0x0000001b +DBTR6_D: .long 0x00000014 +DBTR7_D: .long 0x00000005 +DBTR8_D: .long 0x00000015 +DBTR9_D: .long 0x00000006 +DBTR10_D: .long 0x00000008 +DBTR11_D: .long 0x00000007 +DBTR12_D: .long 0x0000000e +DBTR13_D: .long 0x00000056 +DBTR14_D: .long 0x00000006 +DBTR15_D: .long 0x00000004 +DBTR16_D: .long 0x00150002 +DBTR17_D: .long 0x000c0017 +DBTR18_D: .long 0x00000200 +DBTR19_D: .long 0x00000040 +DBRNK0_D: .long 0x00000001 +DBPDCNT0_D: .long 0x00000001 +DBPDCNT1_D: .long 0x00000001 +DBPDCNT2_D: .long 0x00000000 +DBPDCNT3_D: .long 0x00004010 +DBPDLCK_D: .long 0x0000a55a +DBPDRGA_D: .long 0x00000028 +DBPDRGD_D: .long 0x00017100

+DBADJ0_D: .long 0x00000000 +DBADJ1_D: .long 0x00000000 +DBADJ2_D: .long 0x18061806 +DBRFCNF0_D: .long 0x000001ff +DBRFCNF1_D: .long 0x08001000 +DBRFCNF2_D: .long 0x00000000 +DBCALCNF_D: .long 0x0000ffff +DBRFEN_D: .long 0x00000001 +DBACEN_D: .long 0x00000001

+/*------- DDR-ECC -------*/ +ECD_ECDEN_A: .long ECD_ECDEN +ECD_ECDEN_D: .long 0x00000001 +ECD_INTSR_A: .long ECD_INTSR +ECD_INTSR_D: .long 0xffffffff +ECD_SPACER_A: .long ECD_SPACER +ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING +ECD_MCR_A: .long ECD_MCR +ECD_MCR_D: .long 0x00000001

• .align 2

+exit_ddr:

+#if defined(CONFIG_SH_32BIT)

• /*------- set PMB -------*/
• write32 PASCR_A, PASCR_29BIT_D
• write32 MMUCR_A, MMUCR_D
• /*****************************************************************

• * ent	virt		phys		v	sz	c	wt
  

• * 0	0xa0000000	0x00000000	1	128M	0	1
  

• * 1	0xa8000000	0x48000000	1	128M	0	1
  

• * 5	0x88000000	0x48000000	1	128M	1	1
  

• */
  

• write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
• write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
• write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
• write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
• write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
• write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
• write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
• write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
• write32 PASCR_A, PASCR_INIT
• mov.l DUMMY_ADDR, r0
• icbi @r0

+#endif /* if defined(CONFIG_SH_32BIT) */

+exit_pmb:

• /* CPU is running on ILRAM? */
• mov r14, r0
• tst #1, r0
• bt 1f
• mov.l _bss_start, r15
• mov.l _spiboot_main, r0

+100: bsrf r0

• nop
• .align 2

+_spiboot_main: .long (spiboot_main - (100b + 4)) +_bss_start: .long bss_start

+1:

• write32 CCR_A, CCR_D
• rts

• nop
  

• .align 4

+#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)

+PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_NOT_USE_D: .long 0x00000000

+PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)

+/* ppn ub v s1 s0 c wt */ +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)

+PASCR_A: .long 0xff000070 +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */

+CCR_A: .long CCR +CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c new file mode 100644 index 0000000..abf1135 --- /dev/null +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -0,0 +1,436 @@ +/*

• • Copyright (C) 2011 Renesas Solutions Corp.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spi_flash.h>

+int checkboard(void) +{

• puts("BOARD: R0P7757LC0030RL board\n");
• return 0;

+}

+static void init_gctrl(void) +{

• unsigned long graofst;
• graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
• writel(graofst | 0x20000f00, GCTRL_GRACR3);

+}

+static int init_pcie_bridge_from_spi(void *buf, size_t size) +{

• struct spi_flash *spi;
• int ret;
• unsigned long pcie_addr;
• spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
• if (!spi) {

• printf("%s: spi_flash probe error.\n", __func__);
  

• return 1;
  

• }
• if (is_sh7757_b0())

• pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
  

• else

• pcie_addr = SH7757LCR_PCIEBRG_ADDR;
  

• ret = spi_flash_read(spi, pcie_addr, size, buf);
• if (ret) {

• printf("%s: spi_flash read error.\n", __func__);
  

• spi_flash_free(spi);
  

• return 1;
  

• }
• spi_flash_free(spi);
• return 0;

+}

+static void init_pcie_bridge(void) +{

• int i;
• unsigned char *data;
• unsigned short tmp;
• unsigned long pcie_size;
• if (!(readw(PCIEBRG_CTRL_H8S) & 0x0001))

• return;
  

• if (is_sh7757_b0())

• pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
  

• else

• pcie_size = SH7757LCR_PCIEBRG_SIZE;
  

• data = malloc(pcie_size);
• if (!data) {

• printf("%s: malloc error.\n", __func__);
  

• return;
  

• }
• if (init_pcie_bridge_from_spi(data, pcie_size)) {

• free(data);
  

• return;
  

• }
• if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&

•    data[3] == 0xff) {
  

• free(data);
  

• printf("%s: skipped initialization\n", __func__);
  

• return;
  

• }
• writew(0xa501, PCIEBRG_CTRL_H8S); /* reset */
• writew(0x0000, PCIEBRG_CP_CTRL);
• writew(0x0000, PCIEBRG_CP_ADDR);
• for (i = 0; i < pcie_size; i += 2) {

• tmp = (data[i] << 8) | data[i + 1];
  

• writew(tmp, PCIEBRG_CP_DATA);
  

• }
• writew(0xa500, PCIEBRG_CTRL_H8S); /* start */
• if (!is_sh7757_b0())

• writel(0x00000001, PCIE_PBICTL3);
  

• free(data);

+}

+static void init_usb_phy(void) +{

• writew(0x0100, USB0_PHY_RESET); /* set reset */
• /* port0 = USB0, port1 = USB1 */
• writew(0x0002, USB0_PHY_PORTSEL);
• writel(0x0001, USB1_PORT1SEL); /* port1 = Host */
• writew(0x0111, USB0_PHY_RESET); /* clear reset */
• writew(0x4000, USB0_SUSPMODE);
• writew(0x4000, USB1_SUSPMODE);

+#if defined(__LITTLE_ENDIAN)

• writel(0x00000000, USB1_EHCIDATAC);
• writel(0x00000000, USB1_OHCIDATAC);

+#endif +}

+static void mac_string_to_hex(unsigned char *mac, char *mac_string) +{

• int i;
• char *s, *e;
• s = mac_string;
• for (i = 0; i < 6; i++) {

• mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
  

• if (s)
  

• 	s = (*e) ? e + 1 : e;
  

• }

+}

Please use eth_parse_enetaddr.

+static void set_mac_to_sh_eth_register(int channel, char *mac_string) +{ +#define SH_ETH_BASE 0xfef00000 +#define MALR(port) (SH_ETH_BASE + 0x800 * (port) + 0x01c8) +#define MAHR(port) (SH_ETH_BASE + 0x800 * (port) + 0x01c0)

• unsigned char mac[6];
• unsigned long val;
• mac_string_to_hex(mac, mac_string);
• val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
• writel(val, MAHR(channel));
• val = (mac[4] << 8) | mac[5];
• writel(val, MALR(channel));

+}

+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) +{ +#define SH_GIGA_ETH_BASE 0xfee00000 +#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) +#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)

• unsigned char mac[6];
• unsigned long val;
• mac_string_to_hex(mac, mac_string);
• val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
• writel(val, GIGA_MAHR(channel));
• val = (mac[4] << 8) | mac[5];
• writel(val, GIGA_MALR(channel));

+}

+/*****************************************************************

• • This PMB must be set on this timing. The lowlevel_init is run on
• • Area 0(phys 0x00000000), so we have to map it.
• • The new PMB table is following:
• • ent virt phys v sz c wt
• • 0 0xa0000000 0x40000000 1 128M 0 1
• • 1 0xa8000000 0x48000000 1 128M 0 1
• • 2 0xb0000000 0x50000000 1 128M 0 1
• • 3 0xb8000000 0x58000000 1 128M 0 1
• • 4 0x80000000 0x40000000 1 128M 1 1
• • 5 0x88000000 0x48000000 1 128M 1 1
• • 6 0x90000000 0x50000000 1 128M 1 1
• • 7 0x98000000 0x58000000 1 128M 1 1
• */

+static void set_pmb_on_board_init(void) +{

• /* clear ITLB */
• writel(0x00000004, 0xff000010);
• /* delete PMB for SPIBOOT */
• writel(0, PMB_ADDR_BASE(0));
• writel(0, PMB_DATA_BASE(0));
• /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
• /* ppn ub v s1 s0 c wt */
• writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
• writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
• writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
• writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
• writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
• writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
• writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
• writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
• writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
• writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
• writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
• writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));

+}

+int board_init(void) +{

• set_pmb_on_board_init();
• /* enable RMII's MDIO (disable GRMII's MDIO) */
• writel(0x00030000, GETHER_GBECONT);
• init_gctrl();
• init_usb_phy();
• return 0;

+}

+int dram_init(void) +{

• DECLARE_GLOBAL_DATA_PTR;
• gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
• printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
• printf(" Physical address\n");
• printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",

• SH7757LCR_SDRAM_PHYS_TOP,
  

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
  

• printf(" 0x%08x - 0x%08x : No Access Area\n",

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
  

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
  

• printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
  

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
  

• 	SH7757LCR_SDRAM_DVC_SIZE - 1);
  

• printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
  

• SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
  

• return 0;

+}

+static int get_sh_eth_mac_raw(unsigned char *buf, int size) +{

• struct spi_flash *spi;
• int ret;
• spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
• if (spi == NULL) {

• printf("%s: spi_flash probe error.\n", __func__);
  

• return 1;
  

• }
• ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
• if (ret) {

• printf("%s: spi_flash read error.\n", __func__);
  

• spi_flash_free(spi);
  

• return 1;
  

• }
• spi_flash_free(spi);

+}

+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) +{

• struct spi_flash *spi;
• int ret;
• memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],

• SH7757LCR_ETHERNET_MAC_SIZE);
  

• mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
• return 0;

+}

+static void init_ethernet_mac(void) +{

• char mac_string[64];
• char env_string[64];
• int i;
• unsigned char *buf;
• buf = malloc(256);

Please add NULL check.

• get_sh_eth_mac_raw(buf, 256);
• /* Fast Ethernet */
• for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {

• get_sh_eth_mac(i, mac_string, buf);
  

• if (i == 0)
  

• 	setenv("ethaddr", mac_string);
  

• else {
  

• 	sprintf(env_string, "eth%daddr", i);
  

• 	setenv(env_string, mac_string);
  

• }
  

• set_mac_to_sh_eth_register(i, mac_string);
  

• }
• /* Gigabit Ethernet */
• for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {

• get_sh_eth_mac(i + 2, mac_string, buf);
  

• sprintf(env_string, "eth%daddr", i + 2);
  

I think that you should use i + SH7757LCR_ETHERNET_NUM_CH.

• setenv(env_string, mac_string);
  

• set_mac_to_sh_giga_eth_register(i, mac_string);
  

• }
• free(buf);

+}

+static void init_pcie(void) +{

• writel(0x00000ff2, PCIE_LADMSK0);
• writel(0x00000001, PCIE_BARMAP0);
• writel(0xffcaa000, PCIE_LAD0);
• writel(0x00030000, PCIE_ENDICTL0);
• writel(0x00000003, PCIE_ENDICTL1);
• writel(0x00000004, PCIE_PBICTL2);

+}

+static void finish_spiboot(void) +{

• /*

• *  SH7757 B0 does not use LBSC.
  

• *  So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
  

• *  This setting is not cleared by manual reset, So we have to set it
  

• *  to 0.
  

• */
  

• writel(0x00000000, GCTRL_SPIBOOTCAN);

+}

+int board_late_init(void) +{

• init_ethernet_mac();
• init_pcie_bridge();
• init_pcie();
• finish_spiboot();
• return 0;

+}

+int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{

• unsigned long graofst;
• writel(0xfedcba98, GCTRL_WPROTECT);
• graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
• writel(graofst | 0xa0000f00, GCTRL_GRACR3);
• return 0;

+}

+U_BOOT_CMD(

• sh_g200, 1, 1, do_sh_g200,
• "enable sh-g200",
• "enable SH-G200 bus (disable PCIe-G200)"

+);

+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{

• int i, ret;
• char mac_string[256];
• struct spi_flash *spi;
• unsigned char *buf;
• if (argc != 5) {

• buf = malloc(256);
  

please add NULL check.

• get_sh_eth_mac_raw(buf, 256);
  

• /* print current MAC address */
  

• for (i = 0; i < 4; i++) {
  

• 	get_sh_eth_mac(i, mac_string, buf);
  

• 	if (i < 2)
  

• 		printf(" ETHERC ch%d = %s\n", i, mac_string);
  

• 	else
  

• 		printf("GETHERC ch%d = %s\n", i-2, mac_string);
  

• }
  

• free(buf);
  

• return 0;
  

• }
• /* new setting */
• memset(mac_string, 0xff, sizeof(mac_string));
• sprintf(mac_string, "%s\t%s\t%s\t%s",

• argv[1], argv[2], argv[3], argv[4]);
  

• /* write MAC data to SPI rom */
• spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
• if (!spi) {

• printf("%s: spi_flash probe error.\n", __func__);
  

• return 1;
  

• }
• ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,

• 		SH7757LCR_SPI_SECTOR_SIZE);
  

• if (ret) {

• printf("%s: spi_flash erase error.\n", __func__);
  

• return 1;
  

• }
• ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,

• 		sizeof(mac_string), mac_string);
  

• if (ret) {

• printf("%s: spi_flash write error.\n", __func__);
  

• spi_flash_free(spi);
  

• return 1;
  

• }
• spi_flash_free(spi);
• puts("The writing of the MAC address to SPI ROM was completed.\n");
• return 0;

+}

+U_BOOT_CMD(

• write_mac, 5, 1, do_write_mac,
• "write MAC address for ETHERC/GETHERC",
• "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"

+); diff --git a/board/renesas/sh7757lcr/spi-boot.c b/board/renesas/sh7757lcr/spi-boot.c new file mode 100644 index 0000000..44cc278 --- /dev/null +++ b/board/renesas/sh7757lcr/spi-boot.c @@ -0,0 +1,111 @@ +/*

• • Copyright (C) 2011 Renesas Solutions Corp.
• • This file is subject to the terms and conditions of the GNU Lesser
• • General Public License. See the file "COPYING.LIB" in the main
• • directory of this archive for more details.
• */

+#include <common.h>

+#define CONFIG_RAM_BOOT_PHYS 0x4ef80000 +#if defined(CONFIG_SH7757_OFFSET_SPI) +#define CONFIG_SPI_ADDR 0x00010000 +#else +#define CONFIG_SPI_ADDR 0x00000000 +#endif +#define CONFIG_SPI_LENGTH 0x00030000 +#define CONFIG_RAM_BOOT 0x8ef80000

+#define SPIWDMADR 0xFE001018 +#define SPIWDMCNTR 0xFE001020 +#define SPIDMCOR 0xFE001028 +#define SPIDMINTSR 0xFE001188 +#define SPIDMINTMR 0xFE001190

+#define SPIDMINTSR_DMEND 0x00000004

+#define TBR 0xFE002000 +#define RBR 0xFE002000

+#define CR1 0xFE002008 +#define CR2 0xFE002010 +#define CR3 0xFE002018 +#define CR4 0xFE002020

+/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01

+/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SPI_CPOL 0x20 +#define SPI_CPHA 0x10 +#define SPI_L1M0 0x08

+/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_SSS 0x01

+#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val +#define spi_read(addr) (*(volatile unsigned long *)(addr))

+/* M25P80 */ +#define M25_READ 0x03

+#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) +static void __uses_spiboot2 spi_reset(void) +{

• spi_write(0xfe, CR1);
• spi_write(0, SPIDMCOR);
• spi_write(0x00, CR1);
• spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
• spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);

+}

+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,

• 			   unsigned long len)
  

+{

• volatile unsigned long i;
• spi_write(M25_READ, TBR);
• spi_write((addr >> 16) & 0xFF, TBR);
• spi_write((addr >> 8) & 0xFF, TBR);
• spi_write(addr & 0xFF, TBR);
• spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
• spi_write(buf, SPIWDMADR);
• spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
• spi_write(1, SPIDMCOR);
• spi_write(0xff, CR3);
• spi_write(spi_read(CR1) | SPI_SSDB, CR1);
• spi_write(spi_read(CR1) | SPI_SSA, CR1);
• while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))

• ;
  

+}

+void __uses_spiboot2 spiboot_main(void) +{

• void (*_start)(void) = CONFIG_SYS_TEXT_BASE;
• spi_reset();
• spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,

• 	CONFIG_SPI_LENGTH);
  

• _start();

+}

diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds new file mode 100644 index 0000000..6255649 --- /dev/null +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -0,0 +1,101 @@ +/*

• • Copyright (C) 2007
• • Nobuhiro Iwamatsu iwamatsu@nigauri.org
• • Copyright (C) 2008-2009
• • Yoshihiro Shimoda shimoda.yoshihiro@renesas.com

Please update your copyright.

• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start)

+SECTIONS +{

• /*

• * entry and reloct_dst will be provided via ldflags
  

• */
  

• . = .;
• PROVIDE (_ftext = .);
• PROVIDE (_fcode = .);
• PROVIDE (_start = .);
• .text :
• {

• arch/sh/cpu/sh4/start.o		(.text)
  

• *(.spiboot1.text)
  

• *(.spiboot2.text)
  

• . = ALIGN(8192);
  

• common/env_embedded.o	(.ppcenv)
  

• . = ALIGN(8192);
  

• common/env_embedded.o	(.ppcenvr)
  

• . = ALIGN(8192);
  

• *(.text)
  

• . = ALIGN(4);
  

• } =0xFF
• PROVIDE (_ecode = .);
• .rodata :
• {

• *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  

• . = ALIGN(4);
  

• }
• PROVIDE (_etext = .);
• PROVIDE (_fdata = .);
• .data :
• {

• *(.data)
  

• . = ALIGN(4);
  

• }
• PROVIDE (_edata = .);
• PROVIDE (_fgot = .);
• .got :
• {

• *(.got)
  

• . = ALIGN(4);
  

• }
• PROVIDE (_egot = .);
• PROVIDE (__u_boot_cmd_start = .);
• .u_boot_cmd :
• {

• *(.u_boot_cmd)
  

• . = ALIGN(4);
  

• }
• PROVIDE (__u_boot_cmd_end = .);
• PROVIDE (reloc_dst_end = .);
• /* _reloc_dst_end = .; */
• PROVIDE (bss_start = .);
• PROVIDE (__bss_start = .);
• .bss (NOLOAD) :
• {

• *(.bss)
  

• . = ALIGN(4);
  

• }
• PROVIDE (bss_end = .);
• PROVIDE (_end = .);

+} diff --git a/boards.cfg b/boards.cfg index 0574bb2..417ed1d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -752,6 +752,7 @@ ms7750se sh sh4 ms7750se - ap325rxa sh sh4 ap325rxa renesas - r2dplus sh sh4 r2dplus renesas - r7780mp sh sh4 r7780mp renesas - +sh7757lcr sh sh4 sh7757lcr renesas - sh7763rdp sh sh4 sh7763rdp renesas - sh7785lcr sh sh4 sh7785lcr renesas - sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1 diff --git a/doc/README.sh7757lcr b/doc/README.sh7757lcr new file mode 100644 index 0000000..cae14e0 --- /dev/null +++ b/doc/README.sh7757lcr @@ -0,0 +1,64 @@ +======================================== +Renesas R0P7757LC0030RL board +========================================

+This board specification: +=========================

+The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:

• • SH7757 (SH-4A)
• • DDR3-SDRAM 256MB (with ECC)
• • SPI ROM 8MB
• • 2D Graphic controller
• • Ethernet controller

+configuration for This board: +=============================

+You can select the configuration as follows:

• • make sh7785lcr_config

+This board specific command: +============================

+This board has the following its specific command:

• • sh_g200
• • write_mac

+1. sh_g200

+If we run this command, SH4 can control the G200. +The default setting is that SH4 cannot control the G200.

+2. write_mac

+You can write MAC address to SPI ROM.

• Usage 1) Write MAC address
• write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
• For example)

• => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
  

• *) We have to input the command as a single line
  

•    (without carriage return)
  

• *) We have to reset after input the command.
  

• Usage 2) Show current data
• write_mac
• For example)

• => write_mac
  

•  ETHERC ch0 = 00:00:87:6c:21:80
  

•  ETHERC ch1 = 00:00:87:6c:21:81
  

• GETHERC ch0 = 00:00:87:6c:21:82
  

• GETHERC ch1 = 00:00:87:6c:21:83
  

diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h new file mode 100644 index 0000000..c9dca42 --- /dev/null +++ b/include/configs/sh7757lcr.h @@ -0,0 +1,143 @@ +/*

• • Configuation settings for the sh7757lcr board
• • Copyright (C) 2011 Renesas Solutions Corp.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __SH7757LCR_H +#define __SH7757LCR_H

+#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4A 1 +#define CONFIG_SH_32BIT 1 +#define CONFIG_CPU_SH7757 1 +#define CONFIG_SH7757LCR 1

+#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SF +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MD5SUM +#define CONFIG_MD5 +#define CONFIG_CMD_LOADS

+#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"

+#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS

+/* MEMORY */ +#define SH7757LCR_SDRAM_BASE (0x80000000) +#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) +#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ +#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)

+#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }

+/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF2 1 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE

+#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \

• 			 224 * 1024 * 1024)
  

+#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE

+#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \

• 			 (128 + 16) * 1024 * 1024)
  

+#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)

+/* FLASH */ +#define CONFIG_SYS_NO_FLASH

+/* Ether */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 1 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1

+#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 +#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) +#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI +#define SH7757LCR_ETHERNET_MAC_SIZE 17 +#define SH7757LCR_ETHERNET_NUM_CH 2 +#define BOARD_LATE_INIT 1

+/* Gigabit Ether */ +#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2

+/* SPI */ +#define CONFIG_SH_SPI 1 +#define CONFIG_SH_SPI_BASE 0xfe002000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO 1

+/* SH7757 board */ +#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 +#define SH7757LCR_GRA_OFFSET 0x1f000000 +#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 +#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) +#define SH7757LCR_PCIEBRG_ADDR 0x00090000 +#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)

+/* ENV setting */ +#define CONFIG_ENV_IS_EMBEDDED +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_ADDR (0x00080000) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) +#define CONFIG_EXTRA_ENV_SETTINGS \

• "netboot=bootp; bootm\0"
  

+/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 48000000 +#define CONFIG_SYS_TMU_CLK_DIV 4 +#define CONFIG_SYS_HZ 1000

+#endif /* __SH7757LCR_H */

1.7.1