On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
On Tue, 2017-11-21 at 17:32 +0000, York Sun wrote:
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On 11/21/2017 09:29 AM, Joakim Tjernlund wrote:
On Tue, 2017-11-21 at 17:23 +0000, York Sun wrote:
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On 11/21/2017 09:18 AM, Joakim Tjernlund wrote:
On Tue, 2017-09-12 at 19:56 +0200, Joakim Tjernlund wrote:
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform.
Signed-off-by: Joakim Tjernlund joakim.tjernlund@infinera.com
drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dcd59..4d00b3f26c 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
pci_setup_indirect(hose, cfg_addr, cfg_data);+#ifdef PEX_CCB_DIV
- /* Configure the PCIE controller core clock ratio */
- pci_hose_write_config_dword(hose, dev, 0x440,
((gd->bus_clk / 1000000) *(16 / PEX_CCB_DIV)) / 333);+#endif block_rev = in_be32(&pci->block_rev1); if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2]; /* 0xDC0 */
Ping?
Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ... Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.
I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a Kconfig option and select the divisor by SoC?
No, this is not something that needs Kconfig, just add the PEX_CCB_DIV #define in relevant PPC CPU, like in config_mpc85xx.h
So what should be in Kconfig, and what shouldn't? This is per SoC macro. Sounds like CONFIG_SYS_ in old days.
York