Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v6: Several improvements: - Rename and shrink reset_cntl syscon to pll_cntl. - Reorder include config defines. v5: No changes. v4: No changes. v3: Add cfi-flash defines. v2: Introduce changes suggested by Daniel Schwierzeck: - Split BMIPS support patches. - Add PERF_BASE to cpus. - Merge with "fix ioremap for BCM6358" patch. - Add a custom ioremap.h instead of modifying the generic one.
arch/mips/dts/brcm,bcm6358.dtsi | 98 ++++++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 18 ++++++- arch/mips/mach-bmips/include/ioremap.h | 45 ++++++++++++++++ include/configs/bmips_bcm6358.h | 30 +++++++++++ 4 files changed, 190 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/brcm,bcm6358.dtsi create mode 100644 arch/mips/mach-bmips/include/ioremap.h create mode 100644 include/configs/bmips_bcm6358.h
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi new file mode 100644 index 0000000..48322fb --- /dev/null +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6358"; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@fffe0100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@fffe0120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@fffe1200 { + compatible = "brcm,bcm6358-mc"; + reg = <0xfffe1200 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 4f4d351..03cba72 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -2,7 +2,23 @@ menu "Broadcom MIPS platforms" depends on ARCH_BMIPS
config SYS_SOC - default "none" + default "bcm6358" if SOC_BMIPS_BCM6358 + +choice + prompt "Broadcom MIPS SoC select" + +config SOC_BMIPS_BCM6358 + bool "BMIPS BCM6358 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6358 family including BCM6358 and BCM6359. + +endchoice
choice prompt "Boot mode" diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h new file mode 100644 index 0000000..404690e --- /dev/null +++ b/arch/mips/mach-bmips/include/ioremap.h @@ -0,0 +1,45 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_BMIPS_IOREMAP_H +#define __ASM_MACH_BMIPS_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_bmips_internal_registers(phys_addr_t offset) +{ +#if defined(CONFIG_SOC_BMIPS_BCM6358) + if (offset >= 0xfffe0000) + return 1; +#endif + + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_bmips_internal_registers(offset)) + return (void __iomem *)offset; + + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_bmips_internal_registers((unsigned long)addr); +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_BMIPS_IOREMAP_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h new file mode 100644 index 0000000..5d018a3 --- /dev/null +++ b/include/configs/bmips_bcm6358.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6358_H +#define __CONFIG_BMIPS_BCM6358_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6358_H */