Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

1 Oct 2009

      Hi Bin,
We can know the block transfer complete using IRQSTAT(Transfer
Complete).
But reading & writing in PIO mode takes time for byte by byte transfers
and there is no way to poll that transfer, that's why I have added delay
there.
I can add comment like,
* Wait before last byte transfer complete *\
Is that ok ??
Regards,
 Dipen
-----Original Message-----
From: Bin Meng [mailto:bmeng.cn@gmail.com] 
Sent: Monday, September 28, 2009 4:41 AM
To: Dudhat Dipen-B09055
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Driver
On Thu, Sep 10, 2009 at 9:37 PM, Dipen Dudhat
dipen.dudhat@freescale.com wrote:
...

                  while (size && (!(irqstat & IRQSTAT_TC))) {

                          udelay(100);

                          irqstat = in_be32(&regs->irqstat);

                          databuf = in_le32(&regs->datport);

                          *((uint *)buffer) = databuf;

                          buffer += 4;

                          size -= 4;

                  }

Is the udelay(100) the recommended delay time by the chip manual or
empirical value?
Can you add a comment before the udelay?
Regards,
Bin Meng