Deassert the reset signal and provide the clock for STDMAC core. This is necessary for the USB 2.0 host controllers.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 5 ++++- arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 5 ++++- arch/arm/include/asm/arch-uniphier/sc-regs.h | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c index 00a21f5..fe9936a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c @@ -17,6 +17,9 @@ void clkrst_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif @@ -29,7 +32,7 @@ void clkrst_init(void) tmp |= SC_CLKCTRL_CLK_ETHER; #endif #ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CLK_MIO; + tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC; #endif #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CLK_NAND; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c index 00a21f5..fe9936a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c @@ -17,6 +17,9 @@ void clkrst_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif @@ -29,7 +32,7 @@ void clkrst_init(void) tmp |= SC_CLKCTRL_CLK_ETHER; #endif #ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CLK_MIO; + tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC; #endif #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CLK_NAND; diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h index 1197bb5..daeeec9 100644 --- a/arch/arm/include/asm/arch-uniphier/sc-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h @@ -39,6 +39,7 @@
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) +#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2) @@ -49,6 +50,7 @@ #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) #define SC_CLKCTRL_CLK_ETHER (0x1 << 12) #define SC_CLKCTRL_CLK_MIO (0x1 << 11) +#define SC_CLKCTRL_CLK_STDMAC (0x1 << 10) #define SC_CLKCTRL_CLK_UMC (0x1 << 4) #define SC_CLKCTRL_CLK_NAND (0x1 << 2) #define SC_CLKCTRL_CLK_SBC (0x1 << 1)