This allows to use this code on non Freescale QorIQ boards. If I am right, there are currently only Freescale boards with a QorIQ Soc that is supported by u-boot, that's why this code was located there.
Some other code parts that currently are located in the board/freescale directory could be moved but this is a first patch to discuss trigger the discussion.
It was tested on P2041rdb_SPIFLASH.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- arch/powerpc/cpu/mpc85xx/Makefile | 10 ++++++++-- .../powerpc/cpu/mpc85xx}/p_corenet/Makefile | 0 .../powerpc/cpu/mpc85xx}/p_corenet/law.c | 0 .../powerpc/cpu/mpc85xx}/p_corenet/pci.c | 0 .../powerpc/cpu/mpc85xx}/p_corenet/tlb.c | 20 ++++++++++---------- board/freescale/common/Makefile | 15 ++------------- 6 files changed, 20 insertions(+), 25 deletions(-) rename {board/freescale/common => arch/powerpc/cpu/mpc85xx}/p_corenet/Makefile (100%) rename {board/freescale/common => arch/powerpc/cpu/mpc85xx}/p_corenet/law.c (100%) rename {board/freescale/common => arch/powerpc/cpu/mpc85xx}/p_corenet/pci.c (100%) rename {board/freescale/common => arch/powerpc/cpu/mpc85xx}/p_corenet/tlb.c (92%)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 6776c85..0b76ff5 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -141,6 +141,8 @@ COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
+SUBLIB-$(CONFIG_FSL_CORENET) += p_corenet/libp_corenet.o + COBJS-y += cpu.o COBJS-y += cpu_init.o COBJS-y += cpu_init_early.o @@ -158,12 +160,16 @@ COBJS = $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SUBLIB := $(addprefix $(obj),$(SUBLIB-y)) START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
-$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +$(LIB): $(obj).depend $(OBJS) $(SUBLIB) + $(call cmd_link_o_target, $(OBJS) $(SUBLIB)) + +$(SUBLIB): $(obj).depend + $(MAKE) -C $(dir $(subst $(obj),,$@))
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diff --git a/board/freescale/common/p_corenet/Makefile b/arch/powerpc/cpu/mpc85xx/p_corenet/Makefile similarity index 100% rename from board/freescale/common/p_corenet/Makefile rename to arch/powerpc/cpu/mpc85xx/p_corenet/Makefile diff --git a/board/freescale/common/p_corenet/law.c b/arch/powerpc/cpu/mpc85xx/p_corenet/law.c similarity index 100% rename from board/freescale/common/p_corenet/law.c rename to arch/powerpc/cpu/mpc85xx/p_corenet/law.c diff --git a/board/freescale/common/p_corenet/pci.c b/arch/powerpc/cpu/mpc85xx/p_corenet/pci.c similarity index 100% rename from board/freescale/common/p_corenet/pci.c rename to arch/powerpc/cpu/mpc85xx/p_corenet/pci.c diff --git a/board/freescale/common/p_corenet/tlb.c b/arch/powerpc/cpu/mpc85xx/p_corenet/tlb.c similarity index 92% rename from board/freescale/common/p_corenet/tlb.c rename to arch/powerpc/cpu/mpc85xx/p_corenet/tlb.c index e5cf208..e6204e1 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/p_corenet/tlb.c @@ -64,17 +64,17 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRAM is at 0xfff00000, it covered the 0xfffff000. */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -144,8 +144,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * in cpu_init_f, so we use entry 16 for nand. */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_1M, 1), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* @@ -153,9 +153,9 @@ struct fsl_e_tlb_entry tlb_table[] = { * fetching ucode and ENV from master */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 17, BOOKE_PAGESZ_1M, 1), + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 17, BOOKE_PAGESZ_1M, 1), #endif };
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 75725b4..41c6a14 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -56,23 +56,12 @@ COBJS-$(CONFIG_P5020DS) += ics307_clk.o COBJS-$(CONFIG_P5040DS) += ics307_clk.o COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
-# deal with common files for P-series corenet based devices -SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o - SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) -SUBLIB := $(addprefix $(obj),$(SUBLIB-y)) - -$(LIB): $(obj).depend $(OBJS) $(SUBLIB) - $(call cmd_link_o_target, $(OBJS) $(SUBLIB))
-$(SUBLIB): $(obj).depend - $(MAKE) -C $(dir $(subst $(obj),,$@)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS))
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