No functional change intended. This patch switches from the legacy I2C API to the DM I2C API, so that this code can be used with DM I2C enabled.
Signed-off-by: Stefan Roese sr@denx.de --- drivers/ddr/marvell/axp/ddr3_init.c | 16 +++++++++++----- drivers/ddr/marvell/axp/ddr3_init.h | 2 +- drivers/ddr/marvell/axp/ddr3_spd.c | 16 ++++++++++++++-- 3 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/marvell/axp/ddr3_init.c b/drivers/ddr/marvell/axp/ddr3_init.c index c5aa1ac18f51..a9dcb74cecb7 100644 --- a/drivers/ddr/marvell/axp/ddr3_init.c +++ b/drivers/ddr/marvell/axp/ddr3_init.c @@ -361,12 +361,18 @@ static u32 ddr3_init_main(void) __maybe_unused u32 ddr_width = BUS_WIDTH; __maybe_unused int status; __maybe_unused u32 win_backup[16]; + __maybe_unused struct udevice *udev; + __maybe_unused int ret;
/* SoC/Board special Initializtions */ fab_opt = ddr3_get_fab_opt();
#ifdef CONFIG_SPD_EEPROM - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + ret = i2c_get_chip_for_busnum(0, BUS_WIDTH_ECC_TWSI_ADDR, 1, &udev); + if (ret) { + printf("Cannot find SPD EEPROM\n"); + return MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP; + } #endif
ddr3_print_version(); @@ -438,7 +444,7 @@ static u32 ddr3_init_main(void)
#if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT) ecc = 0; - if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC)) + if (ddr3_check_config(udev, CONFIG_ECC)) ecc = 1; #endif
@@ -483,7 +489,7 @@ static u32 ddr3_init_main(void) * Dynamically Set 32Bit and ECC for AXP (Relevant only for * Marvell DB boards) */ - if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) { + if (ddr3_check_config(udev, CONFIG_BUS_WIDTH)) { ddr_width = 32; DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n"); } @@ -904,7 +910,7 @@ void ddr3_static_mc_init(void) * Notes: Only Available for ArmadaXP/Armada 370 DB boards * Returns: None. */ -int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type) +int ddr3_check_config(struct udevice *udev, MV_CONFIG_TYPE config_type) { #ifdef AUTO_DETECTION_SUPPORT u8 data = 0; @@ -916,7 +922,7 @@ int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type) else offset = 0;
- ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1); + ret = dm_i2c_read(udev, offset, &data, 1); if (!ret) { switch (config_type) { case CONFIG_ECC: diff --git a/drivers/ddr/marvell/axp/ddr3_init.h b/drivers/ddr/marvell/axp/ddr3_init.h index 9a21886ac3e7..a26bd2a120e9 100644 --- a/drivers/ddr/marvell/axp/ddr3_init.h +++ b/drivers/ddr/marvell/axp/ddr3_init.h @@ -101,7 +101,7 @@ void fix_pll_val(u8 target_fab); u32 ddr3_get_fab_opt(void); u32 ddr3_get_cpu_freq(void); u32 ddr3_get_vco_freq(void); -int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type); +int ddr3_check_config(struct udevice *udev, MV_CONFIG_TYPE config_type); u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2, u32 mask2); u32 ddr3_cl_to_valid_cl(u32 cl); diff --git a/drivers/ddr/marvell/axp/ddr3_spd.c b/drivers/ddr/marvell/axp/ddr3_spd.c index dd772e63ab19..4763403c1278 100644 --- a/drivers/ddr/marvell/axp/ddr3_spd.c +++ b/drivers/ddr/marvell/axp/ddr3_spd.c @@ -209,13 +209,19 @@ static u32 ddr3_get_dimm_num(u32 *dimm_addr) /* Read the dimm eeprom */ for (dimm_cur_addr = MAX_DIMM_ADDR; dimm_cur_addr > MIN_DIMM_ADDR; dimm_cur_addr--) { + struct udevice *udev; + data[SPD_DEV_TYPE_BYTE] = 0;
/* Far-End DIMM must be connected */ if ((dimm_num == 0) && (dimm_cur_addr < FAR_END_DIMM_ADDR)) return 0;
- ret = i2c_read(dimm_cur_addr, 0, 1, (uchar *)data, 3); + ret = i2c_get_chip_for_busnum(0, dimm_cur_addr, 1, &udev); + if (ret) + continue; + + ret = dm_i2c_read(udev, 0, data, 3); if (!ret) { if (data[SPD_DEV_TYPE_BYTE] == SPD_MEM_TYPE_DDR3) { dimm_addr[dimm_num] = dimm_cur_addr; @@ -245,9 +251,15 @@ int ddr3_spd_init(MV_DIMM_INFO *info, u32 dimm_addr, u32 dimm_width) __maybe_unused u8 vendor_high, vendor_low;
if (dimm_addr != 0) { + struct udevice *udev; + memset(spd_data, 0, SPD_SIZE * sizeof(u8));
- ret = i2c_read(dimm_addr, 0, 1, (uchar *)spd_data, SPD_SIZE); + ret = i2c_get_chip_for_busnum(0, dimm_addr, 1, &udev); + if (ret) + return MV_DDR3_TRAINING_ERR_TWSI_FAIL; + + ret = dm_i2c_read(udev, 0, spd_data, SPD_SIZE); if (ret) return MV_DDR3_TRAINING_ERR_TWSI_FAIL; }