From: Konstantin Porotchkin kostap@marvell.com
Add support for SoCs based on AP807 die. Remove unused include file for Armada-8020 SoC.
Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---
arch/arm/dts/armada-7040.dtsi | 3 +- arch/arm/dts/armada-8020.dtsi | 37 ---- arch/arm/dts/armada-8040.dtsi | 3 +- arch/arm/dts/armada-ap806-quad.dtsi | 82 -------- arch/arm/dts/armada-ap806.dtsi | 281 +++------------------------- arch/arm/dts/armada-ap807.dtsi | 40 ++++ arch/arm/dts/armada-ap80x-quad.dtsi | 52 +++++ arch/arm/dts/armada-ap80x.dtsi | 211 +++++++++++++++++++++ 8 files changed, 330 insertions(+), 379 deletions(-) delete mode 100644 arch/arm/dts/armada-8020.dtsi delete mode 100644 arch/arm/dts/armada-ap806-quad.dtsi create mode 100644 arch/arm/dts/armada-ap807.dtsi create mode 100644 arch/arm/dts/armada-ap80x-quad.dtsi create mode 100644 arch/arm/dts/armada-ap80x.dtsi
diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi index ee9716a6c6cc..039d30c72a8c 100644 --- a/arch/arm/dts/armada-7040.dtsi +++ b/arch/arm/dts/armada-7040.dtsi @@ -11,7 +11,8 @@ #include <dt-bindings/gpio/gpio.h> #include "armada-common.dtsi" #include "armada-8k.dtsi" -#include "armada-ap806-quad.dtsi" +#include "armada-ap806.dtsi" +#include "armada-ap80x-quad.dtsi"
/* CP110-0 Settings */ #define CP110_NAME cp0 diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi deleted file mode 100644 index 4c71cf35006e..000000000000 --- a/arch/arm/dts/armada-8020.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016- 2021 Marvell International Ltd. - */ - -/* - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-common.dtsi" -#include "armada-8k.dtsi" -#include "armada-ap806-dual.dtsi" - -/* CP110-0 Settings */ -#define CP110_NAME cp0 -#define CP110_NUM 0 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_NUM - -/* CP110-1 Settings */ -#define CP110_NAME cp1 -#define CP110_NUM 1 - -#include "armada-cp110.dtsi" - -#undef CP110_NAME -#undef CP110_NUM - -/ { - model = "Marvell Armada 8020"; - compatible = "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi index 1d77e75d40a9..5123742b8d51 100644 --- a/arch/arm/dts/armada-8040.dtsi +++ b/arch/arm/dts/armada-8040.dtsi @@ -11,7 +11,8 @@ #include <dt-bindings/gpio/gpio.h> #include "armada-common.dtsi" #include "armada-8k.dtsi" -#include "armada-ap806-quad.dtsi" +#include "armada-ap806.dtsi" +#include "armada-ap80x-quad.dtsi"
/* CP110-0 Settings */ #define CP110_NAME cp0 diff --git a/arch/arm/dts/armada-ap806-quad.dtsi b/arch/arm/dts/armada-ap806-quad.dtsi deleted file mode 100644 index ba43a4357b89..000000000000 --- a/arch/arm/dts/armada-ap806-quad.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model = "Marvell Armada AP806 Quad"; - compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@000 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x000>; - enable-method = "psci"; - }; - cpu@001 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x001>; - enable-method = "psci"; - }; - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x100>; - enable-method = "psci"; - }; - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x101>; - enable-method = "psci"; - }; - }; -}; diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index 713c2dba74cd..f432089ab25b 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -1,274 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2020 Marvell International Ltd. */
/* * Device Tree file for Marvell Armada AP806. */
-#include <dt-bindings/interrupt-controller/arm-gic.h> +/* AP806 Settings */ +#define AP_NAME ap806
-/dts-v1/; +#include "armada-ap80x.dtsi"
/ { model = "Marvell Armada AP806"; - compatible = "marvell,armada-ap806"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - psci-area@4000000 { - reg = <0x0 0x4000000 0x0 0x200000>; - no-map; - }; - }; - - ap806 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges;
+ AP_NAME { config-space { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf0000000 0x1000000>; - - gic: interrupt-controller@210000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x280000 0x1000>; - arm,msi-base-spi = <160>; - arm,msi-num-spis = <32>; - }; - gic_v2m1: v2m@290000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x290000 0x1000>; - arm,msi-base-spi = <192>; - arm,msi-num-spis = <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2a0000 0x1000>; - arm,msi-base-spi = <224>; - arm,msi-num-spis = <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2b0000 0x1000>; - arm,msi-base-spi = <256>; - arm,msi-num-spis = <32>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; - }; - - odmi: odmi@300000 { - compatible = "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; - - ap_pinctl: ap-pinctl@6F4000 { - compatible = "marvell,ap806-pinctrl"; - bank-name ="apn-806"; - reg = <0x6F4000 0x10>; - pin-count = <20>; - max-func = <3>; - - ap_i2c0_pins: i2c-pins-0 { - marvell,pins = < 4 5 >; - marvell,function = <3>; - }; - ap_emmc_pins: emmc-pins-0 { - marvell,pins = < 0 1 2 3 4 5 6 7 - 8 9 10 >; - marvell,function = <1>; - }; - }; - - ap_gpio0: gpio@6F5040 { - compatible = "marvell,orion-gpio"; - reg = <0x6F5040 0x40>; - ngpios = <20>; - gpio-controller; - #gpio-cells = <2>; - }; - - xor@400000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - xor@420000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - xor@440000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - xor@460000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible = "marvell,armada-380-spi"; - reg = <0x510600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ap_syscon 3>; - status = "disabled"; - }; - - i2c0: i2c@511000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x511000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; - clocks = <&ap_syscon 3>; - status = "disabled"; - }; - - uart0: serial@512000 { - compatible = "snps,dw-apb-uart"; - reg = <0x512000 0x100>; - reg-shift = <2>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clocks = <&ap_syscon 3>; - status = "disabled"; - clock-frequency = <200000000>; - }; - - uart1: serial@512100 { - compatible = "snps,dw-apb-uart"; - reg = <0x512100 0x100>; - reg-shift = <2>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clocks = <&ap_syscon 3>; - status = "disabled"; - - }; - - ap_sdhci0: sdhci@6e0000 { - compatible = "marvell,armada-8k-sdhci"; - reg = <0x6e0000 0x300>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - dma-coherent; - status = "disabled"; - }; - - ap_syscon: system-controller@6f4000 { - compatible = "marvell,ap806-system-controller", - "syscon"; - #clock-cells = <1>; - clock-output-names = "ap-cpu-cluster-0", - "ap-cpu-cluster-1", - "ap-fixed", "ap-mss"; - reg = <0x6f4000 0x1000>; + sar-reg { + compatible = "marvell,sample-at-reset-common", + "marvell,sample-at-reset-ap806"; + reg = <0x6F8200 0x8>; + sar-driver = "ap806_sar"; + sar-name = "ap806_sar"; + status = "okay"; + }; + + thermal: thermal@6f8084 { + compatible = "marvell,mvebu-thermal", + "marvell,thermal-ext-sensor"; + reg = <0x6f8084 0x12>; + gain = <425>; + offset = <153400>; + divisor = <1000>; + status = "okay"; }; }; }; diff --git a/arch/arm/dts/armada-ap807.dtsi b/arch/arm/dts/armada-ap807.dtsi new file mode 100644 index 000000000000..a5309f34309a --- /dev/null +++ b/arch/arm/dts/armada-ap807.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +/* + * Device Tree file for Marvell Armada AP807. + */ + +/* AP807 Settings */ +#define AP_NAME ap807 + +#include "armada-ap80x.dtsi" + +/ { + model = "Marvell Armada AP807"; + + AP_NAME { + config-space { + sar-reg { + compatible = "marvell,sample-at-reset-common", + "marvell,sample-at-reset-ap807"; + reg = <0x6F8200 0x8>; + sar-driver = "ap807_sar"; + sar-name = "ap807_sar"; + status = "okay"; + }; + + thermal: thermal@6f8084 { + compatible = "marvell,mvebu-thermal", + "marvell,thermal-ext-sensor"; + reg = <0x6f8084 0x12>; + gain = <394>; + offset = <128900>; + divisor = <1000>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-ap80x-quad.dtsi b/arch/arm/dts/armada-ap80x-quad.dtsi new file mode 100644 index 000000000000..1220e986e387 --- /dev/null +++ b/arch/arm/dts/armada-ap80x-quad.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + */ + +/* + * Device Tree file for Marvell Armada AP806/AP807. + */ + +/ { + model = "Marvell Armada AP80X Quad"; + compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@000 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + }; + cpu@001 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x001>; + enable-method = "psci"; + }; + cpu@100 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu@101 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + }; + }; +}; diff --git a/arch/arm/dts/armada-ap80x.dtsi b/arch/arm/dts/armada-ap80x.dtsi new file mode 100644 index 000000000000..8787a872d85e --- /dev/null +++ b/arch/arm/dts/armada-ap80x.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + * + */ + +/* + * Device Tree file for Marvell Armada AP806/AP807. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/dts-v1/; + +/ { + compatible = "marvell,armada-ap806"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + psci-area@4000000 { + reg = <0x0 0x4000000 0x0 0x200000>; + no-map; + }; + }; + + AP_NAME { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + config-space { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x280000 0x1000>; + arm,msi-base-spi = <160>; + arm,msi-num-spis = <32>; + }; + gic_v2m1: v2m@290000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x290000 0x1000>; + arm,msi-base-spi = <192>; + arm,msi-num-spis = <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2a0000 0x1000>; + arm,msi-base-spi = <224>; + arm,msi-num-spis = <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2b0000 0x1000>; + arm,msi-base-spi = <256>; + arm,msi-num-spis = <32>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + }; + + odmi: odmi@300000 { + compatible = "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames = <4>; + reg = <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base = <128>, <136>, <144>, <152>; + }; + + ap_pinctl: ap-pinctl@6F4000 { + compatible = "marvell,ap806-pinctrl"; + bank-name ="apn-806"; + reg = <0x6F4000 0x10>; + pin-count = <20>; + max-func = <3>; + + ap_i2c0_pins: i2c-pins-0 { + marvell,pins = < 4 5 >; + marvell,function = <3>; + }; + ap_emmc_pins: emmc-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 + 8 9 10 12 >; + marvell,function = <1>; + }; + }; + + ap_gpio0: gpio@6F5040 { + compatible = "marvell,orion-gpio"; + reg = <0x6F5040 0x40>; + ngpios = <20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ap_spi0: spi@510600 { + compatible = "marvell,armada-380-spi"; + reg = <0x510600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ap_syscon 3>; + status = "disabled"; + }; + + ap_i2c0: i2c@511000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x511000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + timeout-ms = <1000>; + clocks = <&ap_syscon 3>; + status = "disabled"; + }; + + uart0: serial@512000 { + compatible = "snps,dw-apb-uart"; + reg = <0x512000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&ap_syscon 3>; + status = "disabled"; + clock-frequency = <200000000>; + }; + + uart1: serial@512100 { + compatible = "snps,dw-apb-uart"; + reg = <0x512100 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&ap_syscon 3>; + status = "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x610000 0x1000>, <0x600000 0x1000>; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible = "marvell,armada-8k-sdhci"; + reg = <0x6e0000 0x300>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + status = "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible = "marvell,ap806-system-controller", + "syscon"; + #clock-cells = <1>; + clock-output-names = "ap-cpu-cluster-0", + "ap-cpu-cluster-1", + "ap-fixed", "ap-mss"; + reg = <0x6f4000 0x1000>; + }; + }; + }; +};