[PATCH v1 16/26] colibri_vf: synchronise device tree with linux

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v5.19-rc5.

Please note that this also means that instead of the previous "generic" U-Boot specific carrier board agnostic device tree we are now using the regular one for the Colibri Evaluation (carrier) board V3 (e.g. vf610-colibri-eval-v3.dtb rather than the previous vf610-colibri.dtb).

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com ---

arch/arm/dts/Makefile | 3 +- arch/arm/dts/vf-colibri-eval-v3.dtsi | 152 ++++++ arch/arm/dts/vf-colibri-u-boot.dtsi | 27 - arch/arm/dts/vf-colibri.dtsi | 474 +++++++++++------- arch/arm/dts/vf500-colibri.dts | 13 - .../arm/dts/vf610-colibri-eval-v3-u-boot.dtsi | 90 ++++ arch/arm/dts/vf610-colibri-eval-v3.dts | 13 + arch/arm/dts/vf610-colibri.dts | 13 - arch/arm/dts/vf610-colibri.dtsi | 22 + board/toradex/colibri_vf/MAINTAINERS | 10 +- configs/colibri_vf_defconfig | 2 +- include/dt-bindings/clock/vf610-clock.h | 202 ++++++++ 12 files changed, 774 insertions(+), 247 deletions(-) create mode 100644 arch/arm/dts/vf-colibri-eval-v3.dtsi delete mode 100644 arch/arm/dts/vf-colibri-u-boot.dtsi delete mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi create mode 100644 arch/arm/dts/vf610-colibri-eval-v3.dts delete mode 100644 arch/arm/dts/vf610-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dtsi create mode 100644 include/dt-bindings/clock/vf610-clock.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dcd827d011b..5f8e9b529b8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -727,8 +727,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-cubieboard4.dtb \ sun9i-a80-cx-a99.dtb

-dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ - vf610-colibri.dtb \ +dtb-$(CONFIG_VF610) += vf610-colibri-eval-v3.dtb \ vf610-twr.dtb \ vf610-pcm052.dtb \ vf610-bk4r1.dtb diff --git a/arch/arm/dts/vf-colibri-eval-v3.dtsi b/arch/arm/dts/vf-colibri-eval-v3.dtsi new file mode 100644 index 00000000000..14c411f146f --- /dev/null +++ b/arch/arm/dts/vf-colibri-eval-v3.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + panel: panel { + compatible = "edt,et057090dhu"; + backlight = <&bl>; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */ + vin-supply = <&reg_5v0>; + }; +}; + +&bl { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&reg_3v3>; + status = "okay"; +}; + +&dcu0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dcu0_1>; + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&dspi1 { + status = "okay"; + + mcp2515can: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&reg_module_3v3 { + vin-supply = <&reg_3v3>; +}; + +&tcon0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <&reg_usbh_vbus>; +}; + +&iomuxc { + vf610-colibri { + pinctrl_can_int: can_int { + fsl,pins = < + VF610_PAD_PTB21__GPIO_43 0x22ed + >; + }; + }; +}; diff --git a/arch/arm/dts/vf-colibri-u-boot.dtsi b/arch/arm/dts/vf-colibri-u-boot.dtsi deleted file mode 100644 index 2294ee9551e..00000000000 --- a/arch/arm/dts/vf-colibri-u-boot.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 - -/ { - soc { - u-boot,dm-pre-reloc; - }; -}; - -&aips0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_ddr { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&uart0 { - u-boot,dm-pre-reloc; -}; - -&dcu0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi index 9de4b28e870..cc1e069c44e 100644 --- a/arch/arm/dts/vf-colibri.dtsi +++ b/arch/arm/dts/vf-colibri.dtsi @@ -1,248 +1,350 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2019 Toradex AG + * Copyright 2014-2020 Toradex + * */

-/dts-v1/; -#include "vf.dtsi" -#include "vf610-pinfunc.h" - / { - chosen { - stdout-path = &uart0; + aliases { + ethernet0 = &fec1; + ethernet1 = &fec0; };

- aliases { - usb0 = &ehci0; /* required for ums */ - display1 = &dcu0; + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + pwms = <&pwm0 0 5000000 0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + status = "disabled"; };

- reg_usbh_vbus: regulator-usbh-vbus { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */ + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; };

+&adc0 { + status = "okay"; + vref-supply = <&reg_module_3v3_avdd>; +}; + +&adc1 { + status = "okay"; + vref-supply = <&reg_module_3v3_avdd>; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan0>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&clks { + assigned-clocks = <&clks VF610_CLK_ENET_SEL>, + <&clks VF610_CLK_ENET_TS_SEL>; + assigned-clock-parents = <&clks VF610_CLK_ENET_50M>, + <&clks VF610_CLK_ENET_50M>; +}; + &dspi1 { bus-num = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - spi_cmd: sspi@0 { - reg = <0>; - spi-max-frequency = <50000000>; - }; };

-&ehci0 { - dr_mode = "otg"; - fsl,cdet-gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>; +&edma0 { status = "okay"; };

-&ehci1 { - dr_mode = "host"; +&edma1 { status = "okay"; - vbus-supply = <&reg_usbh_vbus>; };

&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; bus-width = <4>; cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; };

-/* Ethernet */ &fec1 { phy-mode = "rmii"; - phy-handle = <&ethphy1>; + phy-supply = <&reg_module_3v3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <1>; - }; - }; };

&i2c0 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; status = "okay";

- /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t0"; - reg = <0x68>; + nand@0 { + compatible = "fsl,vf610-nfc-nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <32>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; }; };

-&iomuxc { +&pwm0 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ddr>; - - pinctrl_ddr: ddrgrp { - fsl,pins = < - VF610_PAD_DDR_A15__DDR_A_15 0x180 - VF610_PAD_DDR_A14__DDR_A_14 0x180 - VF610_PAD_DDR_A13__DDR_A_13 0x180 - VF610_PAD_DDR_A12__DDR_A_12 0x180 - VF610_PAD_DDR_A11__DDR_A_11 0x180 - VF610_PAD_DDR_A10__DDR_A_10 0x180 - VF610_PAD_DDR_A9__DDR_A_9 0x180 - VF610_PAD_DDR_A8__DDR_A_8 0x180 - VF610_PAD_DDR_A7__DDR_A_7 0x180 - VF610_PAD_DDR_A6__DDR_A_6 0x180 - VF610_PAD_DDR_A5__DDR_A_5 0x180 - VF610_PAD_DDR_A4__DDR_A_4 0x180 - VF610_PAD_DDR_A3__DDR_A_3 0x180 - VF610_PAD_DDR_A2__DDR_A_2 0x180 - VF610_PAD_DDR_A1__DDR_A_1 0x180 - VF610_PAD_DDR_A0__DDR_A_0 0x180 - VF610_PAD_DDR_BA2__DDR_BA_2 0x180 - VF610_PAD_DDR_BA1__DDR_BA_1 0x180 - VF610_PAD_DDR_BA0__DDR_BA_0 0x180 - VF610_PAD_DDR_CAS__DDR_CAS_B 0x180 - VF610_PAD_DDR_CKE__DDR_CKE_0 0x180 - VF610_PAD_DDR_CLK__DDR_CLK_0 0x180 - VF610_PAD_DDR_CS__DDR_CS_B_0 0x180 - VF610_PAD_DDR_D15__DDR_D_15 0x10180 - VF610_PAD_DDR_D14__DDR_D_14 0x10180 - VF610_PAD_DDR_D13__DDR_D_13 0x10180 - VF610_PAD_DDR_D12__DDR_D_12 0x10180 - VF610_PAD_DDR_D11__DDR_D_11 0x10180 - VF610_PAD_DDR_D10__DDR_D_10 0x10180 - VF610_PAD_DDR_D9__DDR_D_9 0x10180 - VF610_PAD_DDR_D8__DDR_D_8 0x10180 - VF610_PAD_DDR_D7__DDR_D_7 0x10180 - VF610_PAD_DDR_D6__DDR_D_6 0x10180 - VF610_PAD_DDR_D5__DDR_D_5 0x10180 - VF610_PAD_DDR_D4__DDR_D_4 0x10180 - VF610_PAD_DDR_D3__DDR_D_3 0x10180 - VF610_PAD_DDR_D2__DDR_D_2 0x10180 - VF610_PAD_DDR_D1__DDR_D_1 0x10180 - VF610_PAD_DDR_D0__DDR_D_0 0x10180 - VF610_PAD_DDR_DQM1__DDR_DQM_1 0x10180 - VF610_PAD_DDR_DQM0__DDR_DQM_0 0x10180 - VF610_PAD_DDR_DQS1__DDR_DQS_1 0x10180 - VF610_PAD_DDR_DQS0__DDR_DQS_0 0x10180 - VF610_PAD_DDR_RAS__DDR_RAS_B 0x180 - VF610_PAD_DDR_WE__DDR_WE_B 0x180 - VF610_PAD_DDR_ODT1__DDR_ODT_0 0x180 - VF610_PAD_DDR_ODT0__DDR_ODT_1 0x180 - VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x180 - VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x180 - VF610_PAD_DDR_RESETB 0x180 - >; - }; + pinctrl-0 = <&pinctrl_pwm0>; +};

- pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x33e2 - VF610_PAD_PTD6__DSPI1_SIN 0x33e1 - VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 - VF610_PAD_PTD8__DSPI1_SCK 0x33e2 - >; - }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +};

- pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB20__GPIO_42 0x219d - >; - }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +};

- pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKOUT 0x30df - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30df - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30df - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30df - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30df - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30df - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30df - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30df - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30df - >; - }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +};

- pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +};

- pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; +&usbdev0 { + disable-over-current; + status = "okay"; +};

- pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x11af - VF610_PAD_PTB11__UART0_RX 0x11af - VF610_PAD_PTB12__UART0_RTS 0x11af - VF610_PAD_PTB13__UART0_CTS 0x11af - >; - }; +&usbh1 { + disable-over-current; + status = "okay"; +};

- pinctrl_usbh1_reg: gpio_usb_vbus { - fsl,pins = < - VF610_PAD_PTD4__GPIO_83 0x22ed - >; - }; +&usbmisc0 { + status = "okay"; };

-&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; +&usbmisc1 { status = "okay"; };

-&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; +&usbphy0 { status = "okay"; };

-&dcu0 { +&usbphy1 { status = "okay"; }; + +&iomuxc { + vf610-colibri { + pinctrl_flexcan0: can0grp { + fsl,pins = < + VF610_PAD_PTB14__CAN0_RX 0x31F1 + VF610_PAD_PTB15__CAN0_TX 0x31F2 + >; + }; + + pinctrl_flexcan1: can1grp { + fsl,pins = < + VF610_PAD_PTB16__CAN1_RX 0x31F1 + VF610_PAD_PTB17__CAN1_TX 0x31F2 + >; + }; + + pinctrl_gpio_ext: gpio_ext { + fsl,pins = < + VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ + VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ + VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ + >; + }; + + pinctrl_dcu0_1: dcu0grp_1 { + fsl,pins = < + VF610_PAD_PTE0__DCU0_HSYNC 0x1902 + VF610_PAD_PTE1__DCU0_VSYNC 0x1902 + VF610_PAD_PTE2__DCU0_PCLK 0x1902 + VF610_PAD_PTE4__DCU0_DE 0x1902 + VF610_PAD_PTE5__DCU0_R0 0x1902 + VF610_PAD_PTE6__DCU0_R1 0x1902 + VF610_PAD_PTE7__DCU0_R2 0x1902 + VF610_PAD_PTE8__DCU0_R3 0x1902 + VF610_PAD_PTE9__DCU0_R4 0x1902 + VF610_PAD_PTE10__DCU0_R5 0x1902 + VF610_PAD_PTE11__DCU0_R6 0x1902 + VF610_PAD_PTE12__DCU0_R7 0x1902 + VF610_PAD_PTE13__DCU0_G0 0x1902 + VF610_PAD_PTE14__DCU0_G1 0x1902 + VF610_PAD_PTE15__DCU0_G2 0x1902 + VF610_PAD_PTE16__DCU0_G3 0x1902 + VF610_PAD_PTE17__DCU0_G4 0x1902 + VF610_PAD_PTE18__DCU0_G5 0x1902 + VF610_PAD_PTE19__DCU0_G6 0x1902 + VF610_PAD_PTE20__DCU0_G7 0x1902 + VF610_PAD_PTE21__DCU0_B0 0x1902 + VF610_PAD_PTE22__DCU0_B1 0x1902 + VF610_PAD_PTE23__DCU0_B2 0x1902 + VF610_PAD_PTE24__DCU0_B3 0x1902 + VF610_PAD_PTE25__DCU0_B4 0x1902 + VF610_PAD_PTE26__DCU0_B5 0x1902 + VF610_PAD_PTE27__DCU0_B6 0x1902 + VF610_PAD_PTE28__DCU0_B7 0x1902 + >; + }; + + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x33e2 + VF610_PAD_PTD6__DSPI1_SIN 0x33e1 + VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 + VF610_PAD_PTD8__DSPI1_SCK 0x33e2 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB20__GPIO_42 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_bl_on: gpio_bl_on { + fsl,pins = < + VF610_PAD_PTC0__GPIO_45 0x22ef + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c0_gpio: i2c0gpiogrp { + fsl,pins = < + VF610_PAD_PTB14__GPIO_36 0x37ff + VF610_PAD_PTB15__GPIO_37 0x37ff + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1182 + VF610_PAD_PTB1__FTM0_CH1 0x1182 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + VF610_PAD_PTB8__FTM1_CH0 0x1182 + VF610_PAD_PTB9__FTM1_CH1 0x1182 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + VF610_PAD_PTB12__UART0_RTS 0x21a2 + VF610_PAD_PTB13__UART0_CTS 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + + pinctrl_usbh1_reg: gpio_usb_vbus { + fsl,pins = < + VF610_PAD_PTD4__GPIO_83 0x22ed + >; + }; + }; +}; diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts deleted file mode 100644 index c83a16fdcb8..00000000000 --- a/arch/arm/dts/vf500-colibri.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2014 Toradex AG - */ - -/dts-v1/; -#include "vf-colibri.dtsi" -#include "vf-colibri-u-boot.dtsi" - -/ { - model = "Toradex Colibri VF50"; - compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500"; -}; diff --git a/arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi b/arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi new file mode 100644 index 00000000000..f67c11b3da3 --- /dev/null +++ b/arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2019-2022 Toradex + */ + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&aips0 { + u-boot,dm-pre-reloc; +}; + +&dcu0 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ddr>; + + pinctrl_ddr: ddrgrp { + fsl,pins = < + VF610_PAD_DDR_A15__DDR_A_15 0x180 + VF610_PAD_DDR_A14__DDR_A_14 0x180 + VF610_PAD_DDR_A13__DDR_A_13 0x180 + VF610_PAD_DDR_A12__DDR_A_12 0x180 + VF610_PAD_DDR_A11__DDR_A_11 0x180 + VF610_PAD_DDR_A10__DDR_A_10 0x180 + VF610_PAD_DDR_A9__DDR_A_9 0x180 + VF610_PAD_DDR_A8__DDR_A_8 0x180 + VF610_PAD_DDR_A7__DDR_A_7 0x180 + VF610_PAD_DDR_A6__DDR_A_6 0x180 + VF610_PAD_DDR_A5__DDR_A_5 0x180 + VF610_PAD_DDR_A4__DDR_A_4 0x180 + VF610_PAD_DDR_A3__DDR_A_3 0x180 + VF610_PAD_DDR_A2__DDR_A_2 0x180 + VF610_PAD_DDR_A1__DDR_A_1 0x180 + VF610_PAD_DDR_A0__DDR_A_0 0x180 + VF610_PAD_DDR_BA2__DDR_BA_2 0x180 + VF610_PAD_DDR_BA1__DDR_BA_1 0x180 + VF610_PAD_DDR_BA0__DDR_BA_0 0x180 + VF610_PAD_DDR_CAS__DDR_CAS_B 0x180 + VF610_PAD_DDR_CKE__DDR_CKE_0 0x180 + VF610_PAD_DDR_CLK__DDR_CLK_0 0x180 + VF610_PAD_DDR_CS__DDR_CS_B_0 0x180 + VF610_PAD_DDR_D15__DDR_D_15 0x10180 + VF610_PAD_DDR_D14__DDR_D_14 0x10180 + VF610_PAD_DDR_D13__DDR_D_13 0x10180 + VF610_PAD_DDR_D12__DDR_D_12 0x10180 + VF610_PAD_DDR_D11__DDR_D_11 0x10180 + VF610_PAD_DDR_D10__DDR_D_10 0x10180 + VF610_PAD_DDR_D9__DDR_D_9 0x10180 + VF610_PAD_DDR_D8__DDR_D_8 0x10180 + VF610_PAD_DDR_D7__DDR_D_7 0x10180 + VF610_PAD_DDR_D6__DDR_D_6 0x10180 + VF610_PAD_DDR_D5__DDR_D_5 0x10180 + VF610_PAD_DDR_D4__DDR_D_4 0x10180 + VF610_PAD_DDR_D3__DDR_D_3 0x10180 + VF610_PAD_DDR_D2__DDR_D_2 0x10180 + VF610_PAD_DDR_D1__DDR_D_1 0x10180 + VF610_PAD_DDR_D0__DDR_D_0 0x10180 + VF610_PAD_DDR_DQM1__DDR_DQM_1 0x10180 + VF610_PAD_DDR_DQM0__DDR_DQM_0 0x10180 + VF610_PAD_DDR_DQS1__DDR_DQS_1 0x10180 + VF610_PAD_DDR_DQS0__DDR_DQS_0 0x10180 + VF610_PAD_DDR_RAS__DDR_RAS_B 0x180 + VF610_PAD_DDR_WE__DDR_WE_B 0x180 + VF610_PAD_DDR_ODT1__DDR_ODT_0 0x180 + VF610_PAD_DDR_ODT0__DDR_ODT_1 0x180 + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x180 + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x180 + VF610_PAD_DDR_RESETB 0x180 + >; + }; +}; + +&pinctrl_ddr { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/vf610-colibri-eval-v3.dts b/arch/arm/dts/vf610-colibri-eval-v3.dts new file mode 100644 index 00000000000..fb661e8a2dc --- /dev/null +++ b/arch/arm/dts/vf610-colibri-eval-v3.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +/dts-v1/; +#include "vf610-colibri.dtsi" +#include "vf-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri VF61 on Colibri Evaluation Board"; + compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; +}; diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts deleted file mode 100644 index 7275fec279f..00000000000 --- a/arch/arm/dts/vf610-colibri.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2014 Toradex AG - */ - -/dts-v1/; -#include "vf-colibri.dtsi" -#include "vf-colibri-u-boot.dtsi" - -/ { - model = "Toradex Colibri VF61"; - compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610"; -}; diff --git a/arch/arm/dts/vf610-colibri.dtsi b/arch/arm/dts/vf610-colibri.dtsi new file mode 100644 index 00000000000..607cec2df86 --- /dev/null +++ b/arch/arm/dts/vf610-colibri.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2014-2020 Toradex + */ + +#include "vf610.dtsi" +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61 COM"; + compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <50000000>; +}; diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 9f18b9a39d4..f821a3334b6 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -3,10 +3,10 @@ M: Marcel Ziswiler marcel.ziswiler@toradex.com W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained -F: board/toradex/colibri_vf/ -F: include/configs/colibri_vf.h -F: configs/colibri_vf_defconfig F: arch/arm/dts/vf-colibri.dtsi -F: arch/arm/dts/vf-colibri-u-boot.dtsi -F: arch/arm/dts/vf500-colibri.dts +F: arch/arm/dts/vf-colibri-eval-v3.dtsi +F: arch/arm/dts/vf610-colibri-eval-v3-u-boot.dtsi F: arch/arm/dts/vf610-colibri.dts +F: board/toradex/colibri_vf/ +F: configs/colibri_vf_defconfig +F: include/configs/colibri_vf.h diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 9dbe6280dd7..febfdbcff05 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x180000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri-eval-v3" CONFIG_TARGET_COLIBRI_VF=y CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_SYS_MEMTEST_START=0x80010000 diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h new file mode 100644 index 00000000000..373644e4674 --- /dev/null +++ b/include/dt-bindings/clock/vf610-clock.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DT_BINDINGS_CLOCK_VF610_H +#define __DT_BINDINGS_CLOCK_VF610_H + +#define VF610_CLK_DUMMY 0 +#define VF610_CLK_SIRC_128K 1 +#define VF610_CLK_SIRC_32K 2 +#define VF610_CLK_FIRC 3 +#define VF610_CLK_SXOSC 4 +#define VF610_CLK_FXOSC 5 +#define VF610_CLK_FXOSC_HALF 6 +#define VF610_CLK_SLOW_CLK_SEL 7 +#define VF610_CLK_FASK_CLK_SEL 8 +#define VF610_CLK_AUDIO_EXT 9 +#define VF610_CLK_ENET_EXT 10 +#define VF610_CLK_PLL1_SYS 11 +#define VF610_CLK_PLL1_PFD1 12 +#define VF610_CLK_PLL1_PFD2 13 +#define VF610_CLK_PLL1_PFD3 14 +#define VF610_CLK_PLL1_PFD4 15 +#define VF610_CLK_PLL2_BUS 16 +#define VF610_CLK_PLL2_PFD1 17 +#define VF610_CLK_PLL2_PFD2 18 +#define VF610_CLK_PLL2_PFD3 19 +#define VF610_CLK_PLL2_PFD4 20 +#define VF610_CLK_PLL3_USB_OTG 21 +#define VF610_CLK_PLL3_PFD1 22 +#define VF610_CLK_PLL3_PFD2 23 +#define VF610_CLK_PLL3_PFD3 24 +#define VF610_CLK_PLL3_PFD4 25 +#define VF610_CLK_PLL4_AUDIO 26 +#define VF610_CLK_PLL5_ENET 27 +#define VF610_CLK_PLL6_VIDEO 28 +#define VF610_CLK_PLL3_MAIN_DIV 29 +#define VF610_CLK_PLL4_MAIN_DIV 30 +#define VF610_CLK_PLL6_MAIN_DIV 31 +#define VF610_CLK_PLL1_PFD_SEL 32 +#define VF610_CLK_PLL2_PFD_SEL 33 +#define VF610_CLK_SYS_SEL 34 +#define VF610_CLK_DDR_SEL 35 +#define VF610_CLK_SYS_BUS 36 +#define VF610_CLK_PLATFORM_BUS 37 +#define VF610_CLK_IPG_BUS 38 +#define VF610_CLK_UART0 39 +#define VF610_CLK_UART1 40 +#define VF610_CLK_UART2 41 +#define VF610_CLK_UART3 42 +#define VF610_CLK_UART4 43 +#define VF610_CLK_UART5 44 +#define VF610_CLK_PIT 45 +#define VF610_CLK_I2C0 46 +#define VF610_CLK_I2C1 47 +#define VF610_CLK_I2C2 48 +#define VF610_CLK_I2C3 49 +#define VF610_CLK_FTM0_EXT_SEL 50 +#define VF610_CLK_FTM0_FIX_SEL 51 +#define VF610_CLK_FTM0_EXT_FIX_EN 52 +#define VF610_CLK_FTM1_EXT_SEL 53 +#define VF610_CLK_FTM1_FIX_SEL 54 +#define VF610_CLK_FTM1_EXT_FIX_EN 55 +#define VF610_CLK_FTM2_EXT_SEL 56 +#define VF610_CLK_FTM2_FIX_SEL 57 +#define VF610_CLK_FTM2_EXT_FIX_EN 58 +#define VF610_CLK_FTM3_EXT_SEL 59 +#define VF610_CLK_FTM3_FIX_SEL 60 +#define VF610_CLK_FTM3_EXT_FIX_EN 61 +#define VF610_CLK_FTM0 62 +#define VF610_CLK_FTM1 63 +#define VF610_CLK_FTM2 64 +#define VF610_CLK_FTM3 65 +#define VF610_CLK_ENET_50M 66 +#define VF610_CLK_ENET_25M 67 +#define VF610_CLK_ENET_SEL 68 +#define VF610_CLK_ENET 69 +#define VF610_CLK_ENET_TS_SEL 70 +#define VF610_CLK_ENET_TS 71 +#define VF610_CLK_DSPI0 72 +#define VF610_CLK_DSPI1 73 +#define VF610_CLK_DSPI2 74 +#define VF610_CLK_DSPI3 75 +#define VF610_CLK_WDT 76 +#define VF610_CLK_ESDHC0_SEL 77 +#define VF610_CLK_ESDHC0_EN 78 +#define VF610_CLK_ESDHC0_DIV 79 +#define VF610_CLK_ESDHC0 80 +#define VF610_CLK_ESDHC1_SEL 81 +#define VF610_CLK_ESDHC1_EN 82 +#define VF610_CLK_ESDHC1_DIV 83 +#define VF610_CLK_ESDHC1 84 +#define VF610_CLK_DCU0_SEL 85 +#define VF610_CLK_DCU0_EN 86 +#define VF610_CLK_DCU0_DIV 87 +#define VF610_CLK_DCU0 88 +#define VF610_CLK_DCU1_SEL 89 +#define VF610_CLK_DCU1_EN 90 +#define VF610_CLK_DCU1_DIV 91 +#define VF610_CLK_DCU1 92 +#define VF610_CLK_ESAI_SEL 93 +#define VF610_CLK_ESAI_EN 94 +#define VF610_CLK_ESAI_DIV 95 +#define VF610_CLK_ESAI 96 +#define VF610_CLK_SAI0_SEL 97 +#define VF610_CLK_SAI0_EN 98 +#define VF610_CLK_SAI0_DIV 99 +#define VF610_CLK_SAI0 100 +#define VF610_CLK_SAI1_SEL 101 +#define VF610_CLK_SAI1_EN 102 +#define VF610_CLK_SAI1_DIV 103 +#define VF610_CLK_SAI1 104 +#define VF610_CLK_SAI2_SEL 105 +#define VF610_CLK_SAI2_EN 106 +#define VF610_CLK_SAI2_DIV 107 +#define VF610_CLK_SAI2 108 +#define VF610_CLK_SAI3_SEL 109 +#define VF610_CLK_SAI3_EN 110 +#define VF610_CLK_SAI3_DIV 111 +#define VF610_CLK_SAI3 112 +#define VF610_CLK_USBC0 113 +#define VF610_CLK_USBC1 114 +#define VF610_CLK_QSPI0_SEL 115 +#define VF610_CLK_QSPI0_EN 116 +#define VF610_CLK_QSPI0_X4_DIV 117 +#define VF610_CLK_QSPI0_X2_DIV 118 +#define VF610_CLK_QSPI0_X1_DIV 119 +#define VF610_CLK_QSPI1_SEL 120 +#define VF610_CLK_QSPI1_EN 121 +#define VF610_CLK_QSPI1_X4_DIV 122 +#define VF610_CLK_QSPI1_X2_DIV 123 +#define VF610_CLK_QSPI1_X1_DIV 124 +#define VF610_CLK_QSPI0 125 +#define VF610_CLK_QSPI1 126 +#define VF610_CLK_NFC_SEL 127 +#define VF610_CLK_NFC_EN 128 +#define VF610_CLK_NFC_PRE_DIV 129 +#define VF610_CLK_NFC_FRAC_DIV 130 +#define VF610_CLK_NFC_INV 131 +#define VF610_CLK_NFC 132 +#define VF610_CLK_VADC_SEL 133 +#define VF610_CLK_VADC_EN 134 +#define VF610_CLK_VADC_DIV 135 +#define VF610_CLK_VADC_DIV_HALF 136 +#define VF610_CLK_VADC 137 +#define VF610_CLK_ADC0 138 +#define VF610_CLK_ADC1 139 +#define VF610_CLK_DAC0 140 +#define VF610_CLK_DAC1 141 +#define VF610_CLK_FLEXCAN0 142 +#define VF610_CLK_FLEXCAN1 143 +#define VF610_CLK_ASRC 144 +#define VF610_CLK_GPU_SEL 145 +#define VF610_CLK_GPU_EN 146 +#define VF610_CLK_GPU2D 147 +#define VF610_CLK_ENET0 148 +#define VF610_CLK_ENET1 149 +#define VF610_CLK_DMAMUX0 150 +#define VF610_CLK_DMAMUX1 151 +#define VF610_CLK_DMAMUX2 152 +#define VF610_CLK_DMAMUX3 153 +#define VF610_CLK_FLEXCAN0_EN 154 +#define VF610_CLK_FLEXCAN1_EN 155 +#define VF610_CLK_PLL7_USB_HOST 156 +#define VF610_CLK_USBPHY0 157 +#define VF610_CLK_USBPHY1 158 +#define VF610_CLK_LVDS1_IN 159 +#define VF610_CLK_ANACLK1 160 +#define VF610_CLK_PLL1_BYPASS_SRC 161 +#define VF610_CLK_PLL2_BYPASS_SRC 162 +#define VF610_CLK_PLL3_BYPASS_SRC 163 +#define VF610_CLK_PLL4_BYPASS_SRC 164 +#define VF610_CLK_PLL5_BYPASS_SRC 165 +#define VF610_CLK_PLL6_BYPASS_SRC 166 +#define VF610_CLK_PLL7_BYPASS_SRC 167 +#define VF610_CLK_PLL1 168 +#define VF610_CLK_PLL2 169 +#define VF610_CLK_PLL3 170 +#define VF610_CLK_PLL4 171 +#define VF610_CLK_PLL5 172 +#define VF610_CLK_PLL6 173 +#define VF610_CLK_PLL7 174 +#define VF610_PLL1_BYPASS 175 +#define VF610_PLL2_BYPASS 176 +#define VF610_PLL3_BYPASS 177 +#define VF610_PLL4_BYPASS 178 +#define VF610_PLL5_BYPASS 179 +#define VF610_PLL6_BYPASS 180 +#define VF610_PLL7_BYPASS 181 +#define VF610_CLK_SNVS 182 +#define VF610_CLK_DAP 183 +#define VF610_CLK_OCOTP 184 +#define VF610_CLK_DDRMC 185 +#define VF610_CLK_WKPU 186 +#define VF610_CLK_TCON0 187 +#define VF610_CLK_TCON1 188 +#define VF610_CLK_CAAM 189 +#define VF610_CLK_CRC 190 +#define VF610_CLK_END 191 + +#endif /* __DT_BINDINGS_CLOCK_VF610_H */