Re: [PATCH] spi: cadence-qspi: use STIG mode for small reads

Hi,

On 11/11/22 16:37, Dhruva Gole wrote:

Fix the issue where some flash chips like cypress S25HS256T for example return the value of the same register once a SPI transaction starts. So for example if read reg of 0x2 is requested and we start reading registers in DAC mode we start reading 4 byte aligned ie. 0x0, 0x1, 0x2 and then 0x3. In such a case the flash chip keeps returning the value of 0x0 even though we actually want the value of 0x2. STIG mode solves the above issue by not issuing a read continuosly for 4 byte aligned data.

Signed-off-by: Dhruva Gole d-gole@ti.com

[...]

Kindly disregard this, and rather look at the v2 patch series I have posted: https://lore.kernel.org/u-boot/20221115114926.174351-1-d-gole@ti.com/

The patch DEPENDs on the new patch I have sent in the v2.