During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in Bypass mode in uboot to enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 +++++++++++++++++- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 213ce3a..a39d08d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -151,7 +151,14 @@ static void erratum_a009203(void) #endif #endif } - +void bypass_smmu(void) +{ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +} void fsl_lsch3_early_init_f(void) { erratum_a008751(); @@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); erratum_a008514(); erratum_a008336(); +#ifdef CONFIG_CHAIN_OF_TRUST + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + if (fsl_check_boot_mode_secure() == 1) + bypass_smmu(); +#endif }
#ifdef CONFIG_SCSI_AHCI_PLAT diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 1fc51e0..06d4856 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -83,6 +83,21 @@ /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 +
/* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)