From: Thierry Reding treding@nvidia.com
This fixes some build errors and warnings caused by inline assembly and pointer to integer cast size mismatches. The inline assembly build error in config_cache() is easy to fix because the code isn't meaningful on 64 bit ARM. For the assembly-level reset_cpu() implementation, provide a version that uses ARMv8 register names, but is otherwise identical.
The remaining warnings about pointer to integer cast size mismatches can be fixed by simply using explicit casts where appropriate, or using long unsigned integers rather than 32-bit sized types where an actual address is stored.
Cc: Tom Warren twarren@nvidia.com Signed-off-by: Thierry Reding treding@nvidia.com --- arch/arm/mach-tegra/ap.c | 4 ++-- arch/arm/mach-tegra/cache.c | 2 ++ arch/arm/mach-tegra/lowlevel_init.S | 15 +++++++++++++++ arch/arm/mach-tegra/pinmux-common.c | 2 +- 4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index cbe9be6f263a..01c15d829fc6 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -135,8 +135,8 @@ static u32 get_odmdata(void) * on BCTs for currently supported SoCs, which are locked down. * If this changes in new chips, we can revisit this algorithm. */ - - u32 bct_start, odmdata; + unsigned long bct_start; + u32 odmdata;
bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR); odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 94f5bce90ec3..0e9cb97832dd 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -21,6 +21,7 @@ #include <asm/arch-tegra/ap.h> #include <asm/arch/gp_padctrl.h>
+#ifndef CONFIG_ARM64 void config_cache(void) { u32 reg = 0; @@ -44,3 +45,4 @@ void config_cache(void) reg |= 2; asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); } +#endif diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index a211bb3b1a60..4fa834ba60e0 100644 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S @@ -11,6 +11,20 @@ #include <version.h> #include <linux/linkage.h>
+#ifdef CONFIG_ARM64 + .align 5 +ENTRY(reset_cpu) + /* get address for global reset register */ + ldr x1, =PRM_RSTCTRL + ldr w3, [x1] + /* force reset */ + orr w3, w3, #0x10 + str w3, [x1] + mov w0, w0 +1: + b 1b +ENDPROC(reset_cpu) +#else .align 5 ENTRY(reset_cpu) ldr r1, rstctl @ get addr for global reset @@ -24,3 +38,4 @@ _loop_forever: rstctl: .word PRM_RSTCTRL ENDPROC(reset_cpu) +#endif diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 912f65e98b06..c9dc58838803 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -78,7 +78,7 @@ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) #endif
-#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset)) +#define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset))
#if defined(CONFIG_TEGRA20)